Lines Matching defs:__I
244 #define __I volatile /*!< Defines 'read only' permissions */
246 #define __I volatile const /*!< Defines 'read only' permissions */
397 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
411 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
412 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
413 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
414 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
415 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
615 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
655 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
716 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
720 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
722 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
723 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
724 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
725 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
726 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
727 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
728 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
729 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
730 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
731 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
732 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
733 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
810 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
955 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
957 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
959 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
960 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
961 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
963 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
964 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
970 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
971 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1102 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1199 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1200 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
