Lines Matching refs:ITM
693 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
694 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
698 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
704 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
705 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
706 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
707 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
709 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
711 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
713 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
715 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
716 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
717 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
719 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
720 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
722 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
723 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
724 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
725 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
726 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
727 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
728 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
729 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
730 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
731 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
732 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
733 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
736 /* ITM Trace Privilege Register Definitions */
737 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
738 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
740 /* ITM Trace Control Register Definitions */
741 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
742 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
744 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
745 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
747 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
748 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
750 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
751 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
753 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
754 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
756 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
757 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
759 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
760 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
762 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
763 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
765 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
766 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
768 /* ITM Integration Write Register Definitions */
769 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
770 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
772 /* ITM Integration Read Register Definitions */
773 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
774 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
776 /* ITM Integration Mode Control Register Definitions */
777 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
778 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
780 /* ITM Lock Status Register Definitions */
781 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
782 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
784 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
785 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
787 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
788 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
964 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1032 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1401 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1413 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1725 \defgroup CMSIS_core_DebugFunctions ITM Functions
1726 \brief Functions that access the ITM debug interface.
1734 /** \brief ITM Send Character
1736 The function transmits a character via the ITM channel 0, and
1746 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1747 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1749 while (ITM->PORT[0].u32 == 0);
1750 ITM->PORT[0].u8 = (uint8_t) ch;
1756 /** \brief ITM Receive Character
1775 /** \brief ITM Check Character
