Lines Matching refs:channel
27 uint8_t channel;
50 #define SPI1_DMA_RX_CFG_A { .channel = 3, .stream = 0 }
51 #define SPI1_DMA_RX_CFG_B { .channel = 3, .stream = 2 }
52 #define SPI1_DMA_TX_CFG_A { .channel = 3, .stream = 3 }
53 #define SPI1_DMA_TX_CFG_B { .channel = 3, .stream = 5 }
56 #define SPI2_DMA_RX_CFG { .channel = 0, .stream = 3 }
57 #define SPI2_DMA_TX_CFG { .channel = 0, .stream = 4 }
60 #define SPI3_DMA_RX_CFG_A { .channel = 0, .stream = 0 }
61 #define SPI3_DMA_RX_CFG_B { .channel = 0, .stream = 2 }
62 #define SPI3_DMA_TX_CFG_A { .channel = 0, .stream = 5 }
63 #define SPI3_DMA_TX_CFG_B { .channel = 0, .stream = 7 }
66 #define SPI4_DMA_RX_CFG_A { .channel = 4, .stream = 0 }
67 #define SPI4_DMA_RX_CFG_B { .channel = 5, .stream = 3 }
68 #define SPI4_DMA_TX_CFG_A { .channel = 4, .stream = 1 }
69 #define SPI4_DMA_TX_CFG_B { .channel = 5, .stream = 4 }
72 #define SPI5_DMA_RX_CFG_A { .channel = 2, .stream = 3 }
73 #define SPI5_DMA_RX_CFG_B { .channel = 7, .stream = 5 }
74 #define SPI5_DMA_TX_CFG_A { .channel = 2, .stream = 4 }
75 #define SPI5_DMA_TX_CFG_B { .channel = 7, .stream = 6 }
78 #define SPI6_DMA_RX_CFG { .channel = 1, .stream = 6 }
79 #define SPI6_DMA_TX_CFG { .channel = 1, .stream = 5 }
