Lines Matching refs:sc
251 struct msk_softc *sc;
253 sc = sc_if->msk_softc;
256 GMAC_WRITE_2 (sc, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD (PHY_ADDR_MARV) | GM_SMI_CT_REG_AD (reg) | GM_SMI_CT_OP_RD);
260 val = GMAC_READ_2 (sc, port, GM_SMI_CTRL);
262 val = GMAC_READ_2 (sc, port, GM_SMI_DATA);
284 struct msk_softc *sc;
286 sc = sc_if->msk_softc;
289 GMAC_WRITE_2 (sc, port, GM_SMI_DATA, val);
290 GMAC_WRITE_2 (sc, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD (PHY_ADDR_MARV) | GM_SMI_CT_REG_AD (reg));
293 if ((GMAC_READ_2 (sc, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY) == 0) {
312 struct msk_softc *sc;
314 sc = sc_if->msk_softc;
344 CSR_WRITE_1 (sc, MR_ADDR (port, GMAC_IRQ_MSK), GM_IS_TX_FF_UR | GM_IS_RX_FF_OR);
377 GMAC_WRITE_2 (sc, port, GM_GP_CTRL, gmac);
379 GMAC_READ_2 (sc, port, GM_GP_CTRL);
386 CSR_WRITE_4 (sc, MR_ADDR (port, GMAC_CTRL), gmac);
398 gmac = GMAC_READ_2 (sc, port, GM_GP_CTRL);
401 GMAC_WRITE_2 (sc, port, GM_GP_CTRL, gmac);
403 GMAC_READ_2 (sc, port, GM_GP_CTRL);
458 struct msk_softc *sc;
460 sc = sc_if->msk_softc;
464 mode = GMAC_READ_2 (sc, port, GM_RX_CTRL);
486 GMAC_WRITE_2 (sc, port, GM_MC_ADDR_H1, mchash[0] & 0xffff );
487 GMAC_WRITE_2 (sc, port, GM_MC_ADDR_H2, (mchash[0] >> 16) & 0xffff );
488 GMAC_WRITE_2 (sc, port, GM_MC_ADDR_H3, mchash[1] & 0xffff );
489 GMAC_WRITE_2 (sc, port, GM_MC_ADDR_H4, (mchash[1] >> 16) & 0xffff );
490 GMAC_WRITE_2 (sc, port, GM_RX_CTRL, mode );
689 struct msk_softc *sc
696 sc->msk_ramsize = CSR_READ_1 (sc, B2_E_0) * 4;
697 DEBUG ((DEBUG_NET, "Marvell Yukon: RAM buffer size : %dKB\n", sc->msk_ramsize));
698 if (sc->msk_ramsize == 0) {
702 sc->msk_pflags |= MSK_FLAG_RAMBUF;
708 sc->msk_rxqsize = (((sc->msk_ramsize * 1024 * 2) / 3) / 1024) * 1024;
709 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize;
710 for (i = 0, next = 0; i < sc->msk_num_port; i++) {
711 sc->msk_rxqstart[i] = next;
712 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1;
713 next = sc->msk_rxqend[i] + 1;
714 sc->msk_txqstart[i] = next;
715 sc->msk_txqend[i] = next + sc->msk_txqsize - 1;
716 next = sc->msk_txqend[i] + 1;
718 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], sc->msk_rxqend[i]));
720 sc->msk_txqsize / 1024, sc->msk_txqstart[i], sc->msk_txqend[i]));
727 struct msk_softc *sc,
738 CSR_WRITE_1 (sc, B0_POWER_CTRL, PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
741 CSR_WRITE_4 (sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
744 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
753 CSR_WRITE_1 (sc, B2_Y2_CLK_GATE, val);
755 val = CSR_PCI_READ_4 (sc, PCI_OUR_REG_1);
757 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
758 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
761 if (sc->msk_num_port > 1) {
767 CSR_PCI_WRITE_4 (sc, PCI_OUR_REG_1, val);
769 switch (sc->msk_hw_id) {
775 CSR_WRITE_2 (sc, B0_CTST, Y2_HW_WOL_OFF);
778 CSR_PCI_WRITE_4 (sc, PCI_OUR_REG_3, 0);
779 our = CSR_PCI_READ_4 (sc, PCI_OUR_REG_4);
782 CSR_PCI_WRITE_4 (sc, PCI_OUR_REG_4, our);
783 our = CSR_PCI_READ_4 (sc, PCI_OUR_REG_5);
785 CSR_PCI_WRITE_4 (sc, PCI_OUR_REG_5, our);
786 CSR_PCI_WRITE_4 (sc, PCI_CFG_REG_1, 0);
791 val = CSR_READ_4 (sc, B2_GP_IO);
793 CSR_WRITE_4 (sc, B2_GP_IO, val);
794 CSR_READ_4 (sc, B2_GP_IO);
799 for (i = 0; i < sc->msk_num_port; i++) {
800 CSR_WRITE_2 (sc, MR_ADDR (i, GMAC_LINK_CTRL), GMLC_RST_SET);
801 CSR_WRITE_2 (sc, MR_ADDR (i, GMAC_LINK_CTRL), GMLC_RST_CLR);
805 val = CSR_PCI_READ_4 (sc, PCI_OUR_REG_1);
807 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
809 if (sc->msk_num_port > 1) {
813 CSR_PCI_WRITE_4 (sc, PCI_OUR_REG_1, val);
818 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
826 CSR_WRITE_1 (sc, B2_Y2_CLK_GATE, val);
827 CSR_WRITE_1 (sc, B0_POWER_CTRL, PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
837 struct msk_softc *sc
844 PciIo = sc->PciIo;
857 CSR_WRITE_1 (sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
870 CSR_WRITE_2 (sc, B0_CTST, CS_MRST_CLR);
876 struct msk_softc *sc
886 PciIo = sc->PciIo;
888 CSR_WRITE_2 (sc, B0_CTST, CS_RST_CLR);
891 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
892 status = CSR_READ_2 (sc, B28_Y2_ASF_HCU_CCSR);
897 CSR_WRITE_2 (sc, B28_Y2_ASF_HCU_CCSR, status);
899 CSR_WRITE_1 (sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
901 CSR_WRITE_2 (sc, B0_CTST, Y2_ASF_DISABLE);
906 CSR_WRITE_2 (sc, B0_CTST, CS_RST_SET);
907 CSR_WRITE_2 (sc, B0_CTST, CS_RST_CLR);
909 clear_pci_errors (sc);
910 switch (sc->msk_bustype) {
913 CSR_PCI_WRITE_4 (sc, PEX_UNC_ERR_STAT, 0xffffffff);
914 val = CSR_PCI_READ_4 (sc, PEX_UNC_ERR_STAT);
916 sc->msk_intrmask &= ~Y2_IS_HW_ERR;
917 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
946 if (sc->msk_bustype == MSK_PCIX_BUS) {
973 msk_phy_power (sc, MSK_PHY_POWERUP);
976 for (i = 0; i < sc->msk_num_port; i++) {
978 CSR_WRITE_4 (sc, MR_ADDR (i, GPHY_CTRL), GPC_RST_SET);
979 CSR_WRITE_4 (sc, MR_ADDR (i, GPHY_CTRL), GPC_RST_CLR);
980 if (sc->msk_hw_id == CHIP_ID_YUKON_UL_2) {
982 CSR_WRITE_4 (sc, MR_ADDR (i, GPHY_CTRL), 0x00105226);
985 CSR_WRITE_4 (sc, MR_ADDR (i, GMAC_CTRL), GMC_RST_SET);
986 CSR_WRITE_4 (sc, MR_ADDR (i, GMAC_CTRL), GMC_RST_CLR);
987 CSR_WRITE_4 (sc, MR_ADDR (i, GMAC_CTRL), GMC_F_LOOPB_OFF);
988 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
989 CSR_WRITE_4 (sc, MR_ADDR (i, GMAC_CTRL), GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | GMC_BYP_RETR_ON);
992 if ((sc->msk_hw_id == CHIP_ID_YUKON_OPT) && (sc->msk_hw_rev == 0)) {
994 CSR_WRITE_4 (sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080);
996 CSR_WRITE_1 (sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
999 CSR_WRITE_2 (sc, B0_CTST, Y2_LED_STAT_ON);
1002 CSR_WRITE_2 (sc, B0_CTST, Y_ULTRA_2_PLUG_IN_GO_EN);
1005 CSR_WRITE_4 (sc, B2_I2C_IRQ, I2C_CLR_IRQ);
1008 CSR_WRITE_1 (sc, B2_TI_CTRL, TIM_STOP);
1009 CSR_WRITE_1 (sc, B2_TI_CTRL, TIM_CLR_IRQ);
1012 CSR_WRITE_1 (sc, B28_DPT_CTRL, DPT_STOP);
1015 CSR_WRITE_1 (sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
1016 CSR_WRITE_1 (sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1019 for (i = 0; i < sc->msk_num_port; i++) {
1020 CSR_WRITE_2 (sc, SELECT_RAM_BUFFER (i, B3_RI_CTRL), RI_RST_SET);
1021 CSR_WRITE_2 (sc, SELECT_RAM_BUFFER (i, B3_RI_CTRL), RI_RST_CLR);
1022 CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_WTO_R1), MSK_RI_TO_53);
1023 CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_WTO_XA1), MSK_RI_TO_53);
1024 CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_WTO_XS1), MSK_RI_TO_53);
1025 CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_RTO_R1), MSK_RI_TO_53);
1026 CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_RTO_XA1), MSK_RI_TO_53);
1027 CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_RTO_XS1), MSK_RI_TO_53);
1028 CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_WTO_R2), MSK_RI_TO_53);
1029 CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_WTO_XA2), MSK_RI_TO_53);
1030 CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_WTO_XS2), MSK_RI_TO_53);
1031 CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_RTO_R2), MSK_RI_TO_53);
1032 CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_RTO_XA2), MSK_RI_TO_53);
1033 CSR_WRITE_1 (sc, SELECT_RAM_BUFFER (i, B3_RI_RTO_XS2), MSK_RI_TO_53);
1037 CSR_WRITE_4 (sc, B0_HWE_IMSK, 0);
1038 CSR_READ_4 (sc, B0_HWE_IMSK);
1039 CSR_WRITE_4 (sc, B0_IMSK, 0);
1040 CSR_READ_4 (sc, B0_IMSK);
1043 gBS->SetMem (sc->msk_stat_ring, sizeof (struct msk_stat_desc) * MSK_STAT_RING_CNT, 0);
1044 sc->msk_stat_cons = 0;
1045 CSR_WRITE_4 (sc, STAT_CTRL, SC_STAT_RST_SET);
1046 CSR_WRITE_4 (sc, STAT_CTRL, SC_STAT_RST_CLR);
1049 PhysAddr = sc->msk_stat_ring_paddr;
1050 CSR_WRITE_4 (sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO (PhysAddr));
1051 CSR_WRITE_4 (sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI (PhysAddr));
1054 CSR_WRITE_2 (sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1);
1055 if ((sc->msk_hw_id == CHIP_ID_YUKON_EC) && (sc->msk_hw_rev == CHIP_REV_YU_EC_A1)) {
1057 CSR_WRITE_2 (sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
1059 CSR_WRITE_1 (sc, STAT_FIFO_WM, 0x21);
1060 CSR_WRITE_1 (sc, STAT_FIFO_ISR_WM, 0x07);
1062 CSR_WRITE_2 (sc, STAT_TX_IDX_TH, 0x0a);
1063 CSR_WRITE_1 (sc, STAT_FIFO_WM, 0x10);
1064 if ((sc->msk_hw_id == CHIP_ID_YUKON_XL) && (sc->msk_hw_rev == CHIP_REV_YU_XL_A0)) {
1065 CSR_WRITE_1 (sc, STAT_FIFO_ISR_WM, 0x04);
1067 CSR_WRITE_1 (sc, STAT_FIFO_ISR_WM, 0x10);
1069 CSR_WRITE_4 (sc, STAT_ISR_TIMER_INI, 0x0190);
1074 CSR_WRITE_4 (sc, STAT_TX_TIMER_INI, MSK_USECS (sc, 1000));
1077 CSR_WRITE_4 (sc, STAT_CTRL, SC_STAT_OP_ON);
1079 CSR_WRITE_1 (sc, STAT_TX_TIMER_CTRL, TIM_START);
1080 CSR_WRITE_1 (sc, STAT_LEV_TIMER_CTRL, TIM_START);
1081 CSR_WRITE_1 (sc, STAT_ISR_TIMER_CTRL, TIM_START);
1157 struct msk_softc *sc;
1161 (VOID**) &sc);
1169 gBS->SetMem (sc, sizeof (struct msk_softc), 0);
1170 sc->PciIo = PciIo;
1175 &sc->OriginalPciAttributes
1178 gBS->FreePool (sc);
1206 sc->RegBase = ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)PciBarResources)->AddrRangeMin;
1208 DEBUG ((DEBUG_NET, "Marvell Yukon: GlobalRegistersBase = 0x%x\n", sc->RegBase));
1221 CSR_WRITE_2 (sc, B0_CTST, CS_RST_CLR);
1224 sc->msk_hw_id = CSR_READ_1 (sc, B2_CHIP_ID);
1225 sc->msk_hw_rev = (CSR_READ_1 (sc, B2_MAC_CFG) >> 4) & 0x0f;
1228 if (sc->msk_hw_id < CHIP_ID_YUKON_XL ||
1229 sc->msk_hw_id > CHIP_ID_YUKON_OPT ||
1230 sc->msk_hw_id == CHIP_ID_YUKON_SUPR ||
1231 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) {
1232 DEBUG ((DEBUG_NET, "Marvell Yukon: unknown device: id=0x%02x, rev=0x%02x\n", sc->msk_hw_id, sc->msk_hw_rev));
1237 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, sc->msk_hw_rev));
1239 sc->msk_process_limit = MSK_PROC_DEFAULT;
1240 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT;
1243 if ((CSR_READ_4 (sc, B2_MAC_1) == 0) && (CSR_READ_4 (sc, B2_MAC_1+4) == 0)) {
1248 CSR_WRITE_2 (sc, B0_CTST, CS_RST_SET);
1249 CSR_WRITE_2 (sc, B0_CTST, CS_RST_CLR);
1250 sc->msk_pmd = CSR_READ_1 (sc, B2_PMD_TYP);
1253 sc->msk_num_port = 1;
1254 if ((CSR_READ_1 (sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
1255 if (!(CSR_READ_1 (sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) {
1256 sc->msk_num_port++;
1261 sc->msk_bustype = MSK_PEX_BUS; /* Only support PCI Express */
1262 sc->msk_expcap = 1;
1264 switch (sc->msk_hw_id) {
1266 sc->msk_clock = 125; /* 125 MHz */
1267 sc->msk_pflags |= MSK_FLAG_JUMBO;
1270 sc->msk_clock = 125; /* 125 MHz */
1271 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM;
1274 sc->msk_clock = 125; /* 125 MHz */
1275 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | MSK_FLAG_AUTOTX_CSUM;
1280 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) {
1281 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM;
1288 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) {
1289 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM;
1293 sc->msk_clock = 100; /* 100 MHz */
1294 sc->msk_pflags |= MSK_FLAG_FASTETHER;
1297 sc->msk_clock = 50; /* 50 MHz */
1298 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | MSK_FLAG_AUTOTX_CSUM;
1299 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
1310 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM;
1314 sc->msk_clock = 156; /* 156 MHz */
1315 sc->msk_pflags |= MSK_FLAG_JUMBO;
1318 sc->msk_clock = 125; /* 125 MHz */
1319 sc->msk_pflags |= MSK_FLAG_JUMBO;
1322 sc->msk_clock = 125; /* 125 MHz */
1323 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2;
1326 sc->msk_clock = 156; /* 156 MHz */
1330 Status = msk_status_dma_alloc (sc);
1336 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU;
1337 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP;
1340 mskc_reset (sc);
1342 mskc_setup_rambuffer (sc);
1351 ScIf->msk_softc = sc;
1352 sc->msk_if[MSK_PORT_A] = ScIf;
1353 Status = mskc_attach_if (sc->msk_if[MSK_PORT_A], MSK_PORT_A);
1360 mmd->pmd = sc->msk_pmd;
1361 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd == 'P') {
1365 if (sc->msk_num_port > 1) {
1373 ScIf->msk_softc = sc;
1374 sc->msk_if[MSK_PORT_B] = ScIf;
1375 Status = mskc_attach_if (sc->msk_if[MSK_PORT_B], MSK_PORT_B);
1382 mmd->pmd = sc->msk_pmd;
1383 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd == 'P') {
1389 *ScData = sc;
1396 (VOID *)sc,
1397 &sc->Timer
1403 Status = gBS->SetTimer (sc->Timer, TimerPeriodic, TICKS_PER_SECOND);
1410 mskc_detach (sc);
1422 sc->OriginalPciAttributes,
1425 gBS->FreePool (sc);
1452 struct msk_softc *sc
1458 if (sc == NULL) {
1464 PciIo = sc->PciIo;
1466 if (sc->msk_if[MSK_PORT_A] != NULL) {
1467 mskc_detach_if (sc->msk_if[MSK_PORT_A]);
1468 gBS->FreePool (sc->msk_if[MSK_PORT_A]);
1469 sc->msk_if[MSK_PORT_A] = NULL;
1471 if (sc->msk_if[MSK_PORT_B] != NULL) {
1472 mskc_detach_if (sc->msk_if[MSK_PORT_B]);
1473 gBS->FreePool (sc->msk_if[MSK_PORT_B]);
1474 sc->msk_if[MSK_PORT_B] = NULL;
1478 CSR_WRITE_4 (sc, B0_IMSK, 0);
1479 CSR_READ_4 (sc, B0_IMSK);
1480 CSR_WRITE_4 (sc, B0_HWE_IMSK, 0);
1481 sc, B0_HWE_IMSK);
1484 CSR_WRITE_2 (sc, B0_CTST, Y2_LED_STAT_OFF);
1487 CSR_WRITE_2 (sc, B0_CTST, CS_RST_SET);
1489 msk_status_dma_free (sc);
1491 if (sc->Timer != NULL) {
1492 gBS->SetTimer (sc->Timer, TimerCancel, 0);
1493 gBS->CloseEvent (sc->Timer);
1495 sc->Timer = NULL;
1503 sc->OriginalPciAttributes,
1514 struct msk_softc *sc
1521 PciIo = sc->PciIo;
1524 EFI_SIZE_TO_PAGES (MSK_STAT_RING_SZ), (VOID**)&sc->msk_stat_ring, 0);
1530 ASSERT (sc->msk_stat_ring != NULL);
1533 Status = PciIo->Map (PciIo, EfiPciIoOperationBusMasterCommonBuffer, sc->msk_stat_ring,
1534 &Length, &sc->msk_stat_ring_paddr, &sc->msk_stat_map);
1547 struct msk_softc *sc
1552 PciIo = sc->PciIo;
1554 if (sc->msk_stat_map) {
1555 PciIo->Unmap (PciIo, sc->msk_stat_map);
1556 if (sc->msk_stat_ring) {
1557 PciIo->FreeBuffer (PciIo, EFI_SIZE_TO_PAGES (MSK_STAT_RING_SZ), sc->msk_stat_ring);
1558 sc->msk_stat_ring = NULL;
1560 sc->msk_stat_map = NULL;
1866 struct msk_softc *sc
1874 for (i = 0; i < sc->msk_num_port; i++) {
1875 if (sc->msk_if[i] != NULL) {
1876 mskc_stop_if (sc->msk_if[i]);
1879 gBS->SetTimer (sc->Timer, TimerCancel, 0);
1882 CSR_WRITE_2 (sc, B0_CTST, CS_RST_SET);
2059 struct msk_softc *sc;
2063 sc = (struct msk_softc *)Context;
2065 if (sc->msk_if[MSK_PORT_A] != NULL && sc->msk_if[MSK_PORT_A]->active) {
2066 e1000phy_tick (sc->msk_if[MSK_PORT_A]->phy_softc);
2068 if (sc->msk_if[MSK_PORT_B] != NULL && sc->msk_if[MSK_PORT_B]->active) {
2069 e1000phy_tick (sc->msk_if[MSK_PORT_B]->phy_softc);
2072 msk_handle_events (sc);
2101 struct msk_softc *sc;
2103 sc = sc_if->msk_softc;
2105 status = CSR_READ_1 (sc, MR_ADDR (sc_if->msk_md.port, GMAC_IRQ_SRC));
2109 CSR_WRITE_4 (sc, MR_ADDR (sc_if->msk_md.port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2113 CSR_WRITE_4 (sc, MR_ADDR (sc_if->msk_md.port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2136 struct msk_softc *sc;
2138 sc = sc_if->msk_softc;
2143 CSR_WRITE_2 (sc, SELECT_RAM_BUFFER (sc_if->msk_md.port, B3_RI_CTRL), RI_CLR_RD_PERR);
2148 CSR_WRITE_2 (sc, SELECT_RAM_BUFFER (sc_if->msk_md.port, B3_RI_CTRL), RI_CLR_WR_PERR);
2153 CSR_WRITE_4 (sc, MR_ADDR (sc_if->msk_md.port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2158 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
2163 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
2170 struct msk_softc *sc
2176 status = CSR_READ_4 (sc, B0_HWE_ISRC);
2180 CSR_WRITE_1 (sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2201 clear_pci_errors (sc);
2216 v32 = CSR_PCI_READ_4 (sc, PEX_UNC_ERR_STAT);
2226 tlphead[i] = CSR_PCI_READ_4 (sc, PEX_HEADER_LOG + i * 4);
2230 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
2231 CSR_WRITE_4 (sc, B0_HWE_IMSK, sc->msk_intrhwemask);
2232 CSR_READ_4 (sc, B0_HWE_IMSK);
2236 CSR_WRITE_1 (sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2237 CSR_PCI_WRITE_4 (sc, PEX_UNC_ERR_STAT, 0xffffffff);
2238 CSR_WRITE_1 (sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2241 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) {
2242 msk_handle_hwerr (sc->msk_if[MSK_PORT_A], status);
2244 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) {
2245 msk_handle_hwerr (sc->msk_if[MSK_PORT_B], status >> 8);
2262 struct msk_softc *sc
2275 if (sc->msk_stat_cons == CSR_READ_2 (sc, STAT_PUT_IDX)) {
2281 cons = sc->msk_stat_cons;
2283 sd = &sc->msk_stat_ring[cons];
2293 sc_if = sc->msk_if[port];
2316 if (sc->msk_if[MSK_PORT_A] != NULL) {
2317 msk_txeof (sc->msk_if[MSK_PORT_A], status & STLE_TXA1_MSKL);
2319 if (sc->msk_if[MSK_PORT_B] != NULL) {
2320 msk_txeof (sc->msk_if[MSK_PORT_B],
2332 if (rxprog > sc->msk_process_limit) {
2337 sc->msk_stat_cons = cons;
2340 msk_rxput (sc->msk_if[MSK_PORT_A]);
2343 msk_rxput (sc->msk_if[MSK_PORT_B]);
2346 return (sc->msk_stat_cons != CSR_READ_2 (sc, STAT_PUT_IDX));
2352 struct msk_softc *sc
2361 Status = CSR_READ_4 (sc, B0_Y2_SP_ISRC2);
2363 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 ||
2364 (Status & sc->msk_intrmask) == 0)
2367 CSR_WRITE_4 (sc, B0_Y2_SP_ICR, 2);
2371 sc_if0 = sc->msk_if[MSK_PORT_A];
2372 sc_if1 = sc->msk_if[MSK_PORT_B];
2388 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2);
2389 CSR_WRITE_4 (sc, B0_IMSK, sc->msk_intrmask);
2390 CSR_READ_4 (sc, B0_IMSK);
2394 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2);
2395 CSR_WRITE_4 (sc, B0_IMSK, sc->msk_intrmask);
2396 CSR_READ_4 (sc, B0_IMSK);
2399 msk_intr_hwerr (sc);
2402 domore = msk_handle_events (sc);
2404 CSR_WRITE_4 (sc, STAT_CTRL, SC_STAT_CLR_IRQ);
2408 CSR_WRITE_4 (sc, B0_Y2_SP_ICR, 2);
2447 IN struct msk_softc *sc;
2449 sc = sc_if->msk_softc;
2458 CSR_WRITE_4 (sc, MR_ADDR (port, GMAC_CTRL), GMC_RST_SET);
2459 CSR_WRITE_4 (sc, MR_ADDR (port, GMAC_CTRL), GMC_RST_CLR);
2460 CSR_WRITE_4 (sc, MR_ADDR (port, GMAC_CTRL), GMC_F_LOOPB_OFF);
2461 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
2462 CSR_WRITE_4 (sc, MR_ADDR (port, GMAC_CTRL), GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | GMC_BYP_RETR_ON);
2469 GMAC_WRITE_2 (sc, port, GM_GP_CTRL, 0);
2472 CSR_READ_1 (sc, MR_ADDR (port, GMAC_IRQ_SRC));
2478 GMAC_WRITE_2 (sc, port, GM_RX_CTRL, GM_RXCR_CRC_DIS);
2481 GMAC_WRITE_2 (sc, port, GM_TX_CTRL, TX_COL_THR (TX_COL_DEF));
2484 GMAC_WRITE_2 (sc, port, GM_TX_FLOW_CTRL, 0xffff);
2487 GMAC_WRITE_2 (sc, port, GM_TX_PARAM,
2493 GMAC_WRITE_2 (sc, port, GM_SERIAL_MODE, gmac);
2497 GMAC_WRITE_2 (sc, port, GM_SRC_ADDR_1L, eaddr[0] | (eaddr[1] << 8));
2498 GMAC_WRITE_2 (sc, port, GM_SRC_ADDR_1M, eaddr[2] | (eaddr[3] << 8));
2499 GMAC_WRITE_2 (sc, port, GM_SRC_ADDR_1H, eaddr[4] | (eaddr[5] << 8));
2500 GMAC_WRITE_2 (sc, port, GM_SRC_ADDR_2L, eaddr[0] | (eaddr[1] << 8));
2501 GMAC_WRITE_2 (sc, port, GM_SRC_ADDR_2M, eaddr[2] | (eaddr[3] << 8));
2502 GMAC_WRITE_2 (sc, port, GM_SRC_ADDR_2H, eaddr[4] | (eaddr[5] << 8));
2505 GMAC_WRITE_2 (sc, port, GM_TX_IRQ_MSK, 0);
2506 GMAC_WRITE_2 (sc, port, GM_RX_IRQ_MSK, 0);
2507 GMAC_WRITE_2 (sc, port, GM_TR_IRQ_MSK, 0);
2510 CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_CTRL_T), GMF_RST_SET);
2511 CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_CTRL_T), GMF_RST_CLR);
2513 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || sc->msk_hw_id == CHIP_ID_YUKON_EX) {
2516 CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_CTRL_T), reg);
2518 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
2520 CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_FL_MSK), 0);
2523 CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
2532 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
2535 CSR_WRITE_2 (sc, MR_ADDR (port, RX_GMF_FL_THR), reg);
2538 CSR_WRITE_4 (sc, MR_ADDR (port, TX_GMF_CTRL_T), GMF_RST_SET);
2539 CSR_WRITE_4 (sc, MR_ADDR (port, TX_GMF_CTRL_T), GMF_RST_CLR);
2540 CSR_WRITE_4 (sc, MR_ADDR (port, TX_GMF_CTRL_T), GMF_OPER_ON);
2547 CSR_WRITE_2 (sc, MR_ADDR (port, RX_GMF_LP_THR), MSK_ECU_LLPP);
2548 CSR_WRITE_2 (sc, MR_ADDR (port, RX_GMF_UP_THR), MSK_ECU_ULPP);
2553 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
2555 reg = CSR_READ_4 (sc, MR_ADDR (port, TX_GMF_EA));
2557 CSR_WRITE_4 (sc, MR_ADDR (port, TX_GMF_EA), reg);
2564 CSR_WRITE_1 (sc, MR_ADDR (port, TXA_CTRL), TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2566 CSR_WRITE_1 (sc, MR_ADDR (port, TXA_CTRL), TXA_ENA_ARB);
2572 CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_txsq, RB_CTRL), RB_RST_SET);
2575 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
2576 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
2577 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
2578 CSR_WRITE_2 (sc, Q_ADDR (sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);
2579 switch (sc->msk_hw_id) {
2581 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {
2583 CSR_WRITE_2 (sc, Q_ADDR (sc_if->msk_txq, Q_AL), MSK_ECU_TXFF_LEV);
2591 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) {
2592 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_F), F_TX_CHK_AUTO_OFF);
2598 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
2599 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
2600 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
2601 CSR_WRITE_2 (sc, Q_ADDR (sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);
2602 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) {
2604 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);
2608 CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_TR_THR), 0x17a);
2609 CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_CTRL_T), RX_TRUNC_ON);
2615 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH);
2624 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
2626 CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_CTRL_T), GMF_RX_MACSEC_FLUSH_OFF);
2631 sc->msk_intrmask |= Y2_IS_PORT_A;
2632 sc->msk_intrhwemask |= Y2_HWE_L1_MASK;
2634 sc->msk_intrmask |= Y2_IS_PORT_B;
2635 sc->msk_intrhwemask |= Y2_HWE_L2_MASK;
2638 CSR_WRITE_4 (sc, B2_IRQM_MSK, sc->msk_intrmask);
2639 if (sc->msk_int_holdoff > 0) {
2641 CSR_WRITE_4 (sc, B2_IRQM_INI, MSK_USECS (sc, sc->msk_int_holdoff));
2642 CSR_WRITE_4 (sc, B2_IRQM_VAL, MSK_USECS (sc, sc->msk_int_holdoff));
2644 CSR_WRITE_1 (sc, B2_IRQM_CTRL, TIM_START);
2646 CSR_WRITE_4 (sc, B0_HWE_IMSK, sc->msk_intrhwemask);
2647 CSR_READ_4 (sc, B0_HWE_IMSK);
2648 CSR_WRITE_4 (sc, B0_IMSK, sc->msk_intrmask);
2649 CSR_READ_4 (sc, B0_IMSK);
2665 struct msk_softc *sc;
2667 sc = sc_if->msk_softc;
2674 CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);
2675 CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_START), sc->msk_rxqstart[port] / 8);
2676 CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_END), sc->msk_rxqend[port] / 8);
2677 CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_WP), sc->msk_rxqstart[port] / 8);
2678 CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_RP), sc->msk_rxqstart[port] / 8);
2680 utpp = (sc->msk_rxqend[port] + 1 - sc->msk_rxqstart[port] - MSK_RB_ULPP) / 8;
2681 ltpp = (sc->msk_rxqend[port] + 1 - sc->msk_rxqstart[port] - MSK_RB_LLPP_B) / 8;
2682 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) {
2685 CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_RX_UTPP), utpp);
2686 CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_rxq, RB_RX_LTPP), ltpp);
2689 CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD);
2690 CSR_READ_1 (sc, RB_ADDR (sc_if->msk_rxq, RB_CTRL));
2693 CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_txq, RB_CTRL), RB_RST_CLR);
2694 CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_txq, RB_START), sc->msk_txqstart[port] / 8);
2695 CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_txq, RB_END), sc->msk_txqend[port] / 8);
2696 CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_txq, RB_WP), sc->msk_txqstart[port] / 8);
2697 CSR_WRITE_4 (sc, RB_ADDR (sc_if->msk_txq, RB_RP), sc->msk_txqstart[port] / 8);
2700 CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD);
2701 CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD);
2702 CSR_READ_1 (sc, RB_ADDR (sc_if->msk_txq, RB_CTRL));
2714 struct msk_softc *sc;
2716 sc = sc_if->msk_softc;
2719 CSR_WRITE_4 (sc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_SET);
2720 CSR_WRITE_4 (sc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_CLR);
2722 CSR_WRITE_4 (sc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_ADDR_LOW_REG), MSK_ADDR_LO (addr));
2723 CSR_WRITE_4 (sc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_ADDR_HI_REG), MSK_ADDR_HI (addr));
2726 CSR_WRITE_2 (sc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_LAST_IDX_REG), count);
2728 CSR_WRITE_4 (sc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_CTRL_REG), PREF_UNIT_OP_ON);
2730 CSR_READ_4 (sc, Y2_PREF_Q_ADDR (qaddr, PREF_UNIT_CTRL_REG));
2744 struct msk_softc *sc;
2746 sc = sc_if->msk_softc;
2747 PciIo = sc->PciIo;
2752 sc->msk_intrmask &= ~Y2_IS_PORT_A;
2753 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK;
2755 sc->msk_intrmask &= ~Y2_IS_PORT_B;
2756 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK;
2758 CSR_WRITE_4 (sc, B0_HWE_IMSK, sc->msk_intrhwemask);
2759 CSR_READ_4 (sc, B0_HWE_IMSK);
2760 CSR_WRITE_4 (sc, B0_IMSK, sc->msk_intrmask);
2761 CSR_READ_4 (sc, B0_IMSK);
2764 val = GMAC_READ_2 (sc, port, GM_GP_CTRL);
2766 GMAC_WRITE_2 (sc, port, GM_GP_CTRL, val);
2768 GMAC_READ_2 (sc, port, GM_GP_CTRL);
2773 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_STOP);
2774 val = CSR_READ_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR));
2777 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_STOP);
2778 val = CSR_READ_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR));
2787 CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_txq, RB_CTRL), RB_RST_SET | RB_DIS_OP_MD);
2790 CSR_WRITE_1 (sc, MR_ADDR (port, GMAC_IRQ_MSK), 0);
2795 CSR_WRITE_1 (sc, MR_ADDR (port, TXA_CTRL), TXA_DIS_ARB);
2798 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_txq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
2801 CSR_WRITE_4 (sc, Y2_PREF_Q_ADDR (sc_if->msk_txq, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_SET);
2804 CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_txq, RB_CTRL), RB_RST_SET);
2807 CSR_WRITE_4 (sc, MR_ADDR (port, TX_GMF_CTRL_T), GMF_RST_SET);
2809 CSR_WRITE_4 (sc, MR_ADDR (port, GMAC_CTRL), GMC_PAUSE_OFF);
2823 CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD);
2825 if (CSR_READ_1 (sc, RB_ADDR (sc_if->msk_rxq, Q_RSL)) == CSR_READ_1 (sc, RB_ADDR (sc_if->msk_rxq, Q_RL))) {
2833 CSR_WRITE_4 (sc, Q_ADDR (sc_if->msk_rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
2835 CSR_WRITE_4 (sc, Y2_PREF_Q_ADDR (sc_if->msk_rxq, PREF_UNIT_CTRL_REG), PREF_UNIT_RST_SET);
2837 CSR_WRITE_1 (sc, RB_ADDR (sc_if->msk_rxq, RB_CTRL), RB_RST_SET);
2839 CSR_WRITE_4 (sc, MR_ADDR (port, RX_GMF_CTRL_T), GMF_RST_SET);
2874 #define MSK_READ_MIB32(x, y) (((UINT32)GMAC_READ_2 (sc, x, (y) + 4)) << 16) + (UINT32)GMAC_READ_2 (sc, x, y)
2887 struct msk_softc *sc;
2889 sc = sc_if->msk_softc;
2893 gmac = GMAC_READ_2 (sc, port, GM_PHY_ADDR);
2894 GMAC_WRITE_2 (sc, port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
2902 GMAC_WRITE_2 (sc, port, GM_PHY_ADDR, gmac);
2915 struct msk_softc *sc;
2917 sc = sc_if->msk_softc;
2921 gmac = GMAC_READ_2 (sc, port, GM_PHY_ADDR);
2922 GMAC_WRITE_2 (sc, port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
2973 GMAC_WRITE_2 (sc, port, GM_PHY_ADDR, gmac);
