Lines Matching refs:mmio_write_32
76 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
84 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
92 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
100 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
108 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
126 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
131 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
136 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
141 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
147 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
227 mmio_write_32(PMUGRF_BASE + PMU_GRF_GPIO0A_P +
231 mmio_write_32(GRF_BASE + GRF_GPIO2A_P +
325 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
351 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
370 mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4,
381 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
385 mmio_write_32(gpio_port[i] + SWPORTA_DR,
387 mmio_write_32(gpio_port[i] + SWPORTA_DDR,
389 mmio_write_32(gpio_port[i] + INTEN, store_gpio[i - 2].inten);
390 mmio_write_32(gpio_port[i] + INTMASK,
392 mmio_write_32(gpio_port[i] + INTTYPE_LEVEL,
394 mmio_write_32(gpio_port[i] + INT_POLARITY,
396 mmio_write_32(gpio_port[i] + DEBOUNCE,
398 mmio_write_32(gpio_port[i] + LS_SYNC,
401 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
