Lines Matching refs:mmio_write_32
476 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
480 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 0);
491 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
513 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
524 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
556 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3),
569 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3),
686 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
710 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), CORES_PM_DISABLE);
779 mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_32K_CNT_MS(30));
780 mmio_write_32(PMU_BASE + PMU_OSC_CNT, CYCL_32K_CNT_MS(30));
783 mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_CNT, CYCL_32K_CNT_MS(3));
786 mmio_write_32(PMU_BASE + PMU_TIMEOUT_CNT, 0x5dc0);
791 mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_24M_CNT_MS(3));
792 mmio_write_32(PMU_BASE + PMU_DDRIO_PWRON_CNT, CYCL_24M_CNT_MS(1));
793 mmio_write_32(PMU_BASE + PMU_CENTER_PWRDN_CNT, CYCL_24M_CNT_MS(1));
794 mmio_write_32(PMU_BASE + PMU_CENTER_PWRUP_CNT, CYCL_24M_CNT_MS(1));
805 mmio_write_32(PMU_BASE + PMU_SCU_L_PWRDN_CNT, CYCL_24M_CNT_MS(5));
806 mmio_write_32(PMU_BASE + PMU_SCU_L_PWRUP_CNT, CYCL_24M_CNT_US(1));
815 mmio_write_32(PMU_BASE + PMU_SCU_B_PWRDN_CNT, CYCL_24M_CNT_US(1));
816 mmio_write_32(PMU_BASE + PMU_SCU_B_PWRUP_CNT, CYCL_24M_CNT_US(1));
817 mmio_write_32(PMU_BASE + PMU_GPU_PWRDN_CNT, CYCL_24M_CNT_US(1));
818 mmio_write_32(PMU_BASE + PMU_GPU_PWRUP_CNT, CYCL_24M_CNT_US(1));
829 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), WMSK_BIT(1));
834 mmio_write_32(GRF_BASE + GRF_SOC_CON4, CCI_FORCE_WAKEUP);
835 mmio_write_32(PMU_BASE + PMU_CCI500_CON,
840 mmio_write_32(PMU_BASE + PMU_ADB400_CON,
873 mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, slp_mode_cfg);
875 mmio_write_32(PMU_BASE + PMU_PLL_CON, PLL_PD_HW);
876 mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON0, EXTERNAL_32K);
877 mmio_write_32(PMUGRF_BASE, IOMUX_CLK_32K); /* 32k iomux */
918 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
930 mmio_write_32(GRF_BASE + GRF_GPIO3A_IOMUX,
932 mmio_write_32(GRF_BASE + GRF_GPIO3B_IOMUX,
934 mmio_write_32(GRF_BASE + GRF_GPIO3C_IOMUX,
938 mmio_write_32(GRF_BASE + GRF_GPIO3A_P, REG_SOC_WMSK | 0);
939 mmio_write_32(GRF_BASE + GRF_GPIO3B_P, REG_SOC_WMSK | 0);
940 mmio_write_32(GRF_BASE + GRF_GPIO3C_P, REG_SOC_WMSK | 0);
950 mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX,
952 mmio_write_32(GRF_BASE + GRF_GPIO2B_IOMUX,
956 mmio_write_32(GRF_BASE + GRF_GPIO2A_P, REG_SOC_WMSK | 0);
957 mmio_write_32(GRF_BASE + GRF_GPIO2B_P, REG_SOC_WMSK | 0);
967 mmio_write_32(GRF_BASE + GRF_GPIO2C_IOMUX,
969 mmio_write_32(GRF_BASE + GRF_GPIO2D_IOMUX,
973 mmio_write_32(GRF_BASE + GRF_GPIO2C_P, REG_SOC_WMSK | 0);
974 mmio_write_32(GRF_BASE + GRF_GPIO2D_P, REG_SOC_WMSK | 0);
984 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX,
986 mmio_write_32(GRF_BASE + GRF_GPIO4D_IOMUX,
990 mmio_write_32(GRF_BASE + GRF_GPIO4C_P, REG_SOC_WMSK | 0);
991 mmio_write_32(GRF_BASE + GRF_GPIO4D_P, REG_SOC_WMSK | 0);
1000 mmio_write_32(GRF_BASE + GRF_GPIO3D_IOMUX,
1002 mmio_write_32(GRF_BASE + GRF_GPIO4A_IOMUX,
1006 mmio_write_32(GRF_BASE + GRF_GPIO3D_P, REG_SOC_WMSK | 0);
1007 mmio_write_32(GRF_BASE + GRF_GPIO4A_P, REG_SOC_WMSK | 0);
1026 mmio_write_32(GRF_BASE + GRF_GPIO2A_P + i * 4,
1028 mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4,
1033 mmio_write_32(GPIO2_BASE + 0x04, gpio_direction[0]);
1034 mmio_write_32(GPIO3_BASE + 0x04, gpio_direction[1]);
1035 mmio_write_32(GPIO4_BASE + 0x04, gpio_direction[2]);
1038 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
1077 mmio_write_32(M0_PARAM_ADDR + PARAM_M0_FUNC, M0_FUNC_SUSPEND);
1141 mmio_write_32(PLAT_RK_UART_BASE + UART_LCR,
1145 mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_save.uart_lcr);
1152 mmio_write_32(PLAT_RK_UART_BASE + UARTSRR,
1156 mmio_write_32(PLAT_RK_UART_BASE + UART_MCR, DIAGNOSTIC_MODE);
1157 mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_lcr | UARTLCR_DLAB);
1158 mmio_write_32(PLAT_RK_UART_BASE + UART_DLL, uart_save.uart_dll);
1159 mmio_write_32(PLAT_RK_UART_BASE + UART_DLH, uart_save.uart_dlh);
1160 mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_save.uart_lcr);
1161 mmio_write_32(PLAT_RK_UART_BASE + UART_IER, uart_save.uart_ier);
1162 mmio_write_32(PLAT_RK_UART_BASE + UART_FCR, UARTFCR_FIFOEN);
1163 mmio_write_32(PLAT_RK_UART_BASE + UART_MCR, uart_save.uart_mcr);
1187 mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL0,
1189 mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL2,
1191 mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL3,
1193 mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL12,
1195 mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL13,
1197 mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL15,
1199 mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL16,
1202 mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL0,
1204 mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL2,
1206 mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL3,
1208 mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL12,
1210 mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL13,
1212 mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL15,
1214 mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL16,
1240 mmio_write_32(GRF_BASE + GRF_SOC_CON(0),
1242 mmio_write_32(GRF_BASE + GRF_SOC_CON(1),
1244 mmio_write_32(GRF_BASE + GRF_SOC_CON(2),
1246 mmio_write_32(GRF_BASE + GRF_SOC_CON(3),
1248 mmio_write_32(GRF_BASE + GRF_SOC_CON(4),
1250 mmio_write_32(GRF_BASE + GRF_SOC_CON(7),
1254 mmio_write_32(GRF_BASE + GRF_DDRC0_CON0 + i * 4,
1257 mmio_write_32(GRF_BASE + GRF_IO_VSEL, REG_SOC_WMSK | store_grf_io_vsel);
1288 mmio_write_32(CRU_BASE + i, store_cru[i / 4]);
1294 mmio_write_32(CRU_BASE + i, store_cru[i / 4]);
1296 mmio_write_32(CRU_BASE + i,
1316 mmio_write_32(WDT0_BASE + i * 4, store_wdt0[i]);
1317 mmio_write_32(WDT1_BASE + i * 4, store_wdt1[i]);
1352 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
1356 mmio_write_32(PMU_BASE + PMU_ADB400_CON,
1420 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3),
1430 mmio_write_32(PMU_BASE + PMU_WAKEUP_STATUS, 0xffffffff);
1431 mmio_write_32(PMU_BASE + PMU_WKUP_CFG4, 0x00);
1433 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
1437 mmio_write_32(PMU_BASE + PMU_CCI500_CON,
1445 mmio_write_32(PMU_BASE + PMU_ADB400_CON,
1523 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1A_IOMUX,
1582 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
1585 mmio_write_32(PMU_BASE + PMU_NOC_AUTO_ENA, NOC_AUTO_ENABLE);
1591 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_SMT, GPIO0A0_SMT_ENABLE);
