Lines Matching defs:val
29 uint32_t i, val;
34 val = mmio_read_32(GRF_BASE + GRF_GPIO4C_IOMUX);
35 if (((val >> GRF_GPIO4C2_IOMUX_SHIFT) &
38 val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK,
40 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val);
43 val = mmio_read_32(GRF_BASE + GRF_GPIO4C_IOMUX);
44 if (((val >> GRF_GPIO4C6_IOMUX_SHIFT) &
47 val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK,
49 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val);
52 val = mmio_read_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX);
53 if (((val >> PMUGRF_GPIO1C3_IOMUX_SHIFT) &
56 val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK,
58 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, val);
61 val = mmio_read_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX);
62 if (((val >> PMUGRF_GPIO0A6_IOMUX_SHIFT) &
65 val = BITS_WITH_WMASK(GRF_IOMUX_GPIO, GRF_IOMUX_2BIT_MASK,
67 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, val);
73 val = mmio_read_32(PWM_BASE + PWM_CTRL(i));
74 if ((val & PWM_ENABLE) != PWM_ENABLE)
77 mmio_write_32(PWM_BASE + PWM_CTRL(i), val & ~PWM_ENABLE);
86 uint32_t i, val;
89 val = mmio_read_32(PWM_BASE + PWM_CTRL(i));
92 mmio_write_32(PWM_BASE + PWM_CTRL(i), val | PWM_ENABLE);
97 val = BITS_WITH_WMASK(PMUGRF_GPIO0A6_IOMUX_PWM,
100 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_IOMUX, val);
104 val = BITS_WITH_WMASK(PMUGRF_GPIO1C3_IOMUX_PWM,
107 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1C_IOMUX, val);
111 val = BITS_WITH_WMASK(GRF_GPIO4C6_IOMUX_PWM,
114 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val);
118 val = BITS_WITH_WMASK(GRF_GPIO4C2_IOMUX_PWM,
121 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX, val);
