Lines Matching refs:x7
31 #define PL350_SMC_DIRECT_CMD_ADDR_CS(ChipSelect) (((ChipSelect) & 0x7) << 23)
61 #define PL350_SMC_SET_CYCLE_NAND_T_REA(t) (((t) & 0x7) << 8)
62 #define PL350_SMC_SET_CYCLE_NAND_T_WP(t) (((t) & 0x7) << 11)
63 #define PL350_SMC_SET_CYCLE_NAND_T_CLR(t) (((t) & 0x7) << 14)
64 #define PL350_SMC_SET_CYCLE_NAND_T_AR(t) (((t) & 0x7) << 17)
65 #define PL350_SMC_SET_CYCLE_NAND_T_RR(t) (((t) & 0x7) << 20)
69 #define PL350_SMC_SET_CYCLE_SRAM_T_CEOE(t) (((t) & 0x7) << 8)
70 #define PL350_SMC_SET_CYCLE_SRAM_T_WP(t) (((t) & 0x7) << 11)
71 #define PL350_SMC_SET_CYCLE_SRAM_T_PC(t) (((t) & 0x7) << 14)
72 #define PL350_SMC_SET_CYCLE_SRAM_T_TR(t) (((t) & 0x7) << 17)
