Lines Matching refs:EP
151 USB_ENDPOINT *Ep;
162 Ep = &Urb->Ep;
163 Ep->BusAddr = BusAddr;
164 Ep->EpAddr = (UINT8) (EpAddr & 0x0F);
165 Ep->Direction = ((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;
166 Ep->DevSpeed = DevSpeed;
167 Ep->MaxPacket = MaxPacket;
168 Ep->Type = Type;
231 SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
242 Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
247 EPType = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;
249 EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;
275 if (Urb->Ep.Direction == EfiUsbDataIn) {
277 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
304 if (Urb->Ep.Direction == EfiUsbDataIn) {
306 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
327 if (Urb->Ep.Direction == EfiUsbDataIn) {
329 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
451 SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
455 Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8) (Urb->Ep.Direction));
510 SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
514 Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8) (Urb->Ep.Direction));
780 SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
784 Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
1144 InputContext->EP[0].EPType = ED_CONTROL_BIDIR;
1147 InputContext->EP[0].MaxPacketSize = 512;
1149 InputContext->EP[0].MaxPacketSize = 64;
1151 InputContext->EP[0].MaxPacketSize = 8;
1157 InputContext->EP[0].AverageTRBLength = 8;
1158 InputContext->EP[0].MaxBurstSize = 0;
1159 InputContext->EP[0].Interval = 0;
1160 InputContext->EP[0].MaxPStreams = 0;
1161 InputContext->EP[0].Mult = 0;
1162 InputContext->EP[0].CErr = 3;
1172 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
1173 InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);
1355 InputContext->EP[0].EPType = ED_CONTROL_BIDIR;
1358 InputContext->EP[0].MaxPacketSize = 512;
1360 InputContext->EP[0].MaxPacketSize = 64;
1362 InputContext->EP[0].MaxPacketSize = 8;
1368 InputContext->EP[0].AverageTRBLength = 8;
1369 InputContext->EP[0].MaxBurstSize = 0;
1370 InputContext->EP[0].Interval = 0;
1371 InputContext->EP[0].MaxPStreams = 0;
1372 InputContext->EP[0].Mult = 0;
1373 InputContext->EP[0].CErr = 3;
1383 InputContext->EP[0].PtrLo = XHC_LOW_32BIT (PhyAddr) | BIT0;
1384 InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (PhyAddr);
1715 InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;
1721 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
1723 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
1729 InputContext->EP[Dci-1].CErr = 3;
1730 InputContext->EP[Dci-1].EPType = ED_BULK_IN;
1732 InputContext->EP[Dci-1].CErr = 3;
1733 InputContext->EP[Dci-1].EPType = ED_BULK_OUT;
1736 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
1746 InputContext->EP[Dci-1].CErr = 0;
1747 InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;
1749 InputContext->EP[Dci-1].CErr = 0;
1750 InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
1755 DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
1760 InputContext->EP[Dci-1].CErr = 3;
1761 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;
1763 InputContext->EP[Dci-1].CErr = 3;
1764 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
1766 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
1767 InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
1777 InputContext->EP[Dci-1].Interval = (UINT32) HighBitSet32 ((UINT32) Interval) + 3;
1784 InputContext->EP[Dci-1].Interval = Interval - 1;
1798 DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd: Unsupport Control EP found, Transfer ring is not allocated.\n"));
1800 DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd: Unknown EP found, Transfer ring is not allocated.\n"));
1812 InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
1813 InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
1918 InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;
1924 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
1926 InputContext->EP[Dci-1].MaxBurstSize = 0x0;
1932 InputContext->EP[Dci-1].CErr = 3;
1933 InputContext->EP[Dci-1].EPType = ED_BULK_IN;
1935 InputContext->EP[Dci-1].CErr = 3;
1936 InputContext->EP[Dci-1].EPType = ED_BULK_OUT;
1939 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
1949 InputContext->EP[Dci-1].CErr = 0;
1950 InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;
1952 InputContext->EP[Dci-1].CErr = 0;
1953 InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;
1958 DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd64: Unsupport ISO EP found, Transfer ring is not allocated.\n"));
1963 InputContext->EP[Dci-1].CErr = 3;
1964 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;
1966 InputContext->EP[Dci-1].CErr = 3;
1967 InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;
1969 InputContext->EP[Dci-1].AverageTRBLength = 0x1000;
1970 InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;
1980 InputContext->EP[Dci-1].Interval = (UINT32) HighBitSet32( (UINT32) Interval) + 3;
1987 InputContext->EP[Dci-1].Interval = Interval - 1;
2001 DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd64: Unsupport Control EP found, Transfer ring is not allocated.\n"));
2003 DEBUG ((EFI_D_INFO, "XhcPeiSetConfigCmd64: Unknown EP found, Transfer ring is not allocated.\n"));
2017 InputContext->EP[Dci-1].PtrLo = XHC_LOW_32BIT (PhyAddr);
2018 InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (PhyAddr);
2084 InputContext->EP[0].MaxPacketSize = MaxPacketSize;
2138 InputContext->EP[0].MaxPacketSize = MaxPacketSize;
