Lines Matching refs:Urb
26 @return Created URB or NULL.
29 URB*
35 URB *Urb;
37 Urb = AllocateZeroPool (sizeof (URB));
38 if (Urb == NULL) {
42 Urb->Signature = XHC_URB_SIG;
44 Urb->Ring = &Xhc->CmdRing;
45 XhcPeiSyncTrsRing (Xhc, Urb->Ring);
46 Urb->TrbNum = 1;
47 Urb->TrbStart = Urb->Ring->RingEnqueue;
48 CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB_TEMPLATE));
49 Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;
50 Urb->TrbEnd = Urb->TrbStart;
52 return Urb;
79 URB *Urb;
96 // Create a new URB, then poll the execution status.
98 Urb = XhcPeiCreateCmdTrb (Xhc, CmdTrb);
99 if (Urb == NULL) {
100 DEBUG ((EFI_D_ERROR, "XhcPeiCmdTransfer: failed to create URB\n"));
105 Status = XhcPeiExecTransfer (Xhc, TRUE, Urb, Timeout);
106 *EvtTrb = Urb->EvtTrb;
108 if (Urb->Result == EFI_USB_NOERROR) {
112 XhcPeiFreeUrb (Xhc, Urb);
119 Create a new URB for a new transaction.
133 @return Created URB or NULL
136 URB*
153 URB *Urb;
155 Urb = AllocateZeroPool (sizeof (URB));
156 if (Urb == NULL) {
160 Urb->Signature = XHC_URB_SIG;
162 Ep = &Urb->Ep;
170 Urb->Request = Request;
171 Urb->Data = Data;
172 Urb->DataLen = DataLen;
173 Urb->Callback = Callback;
174 Urb->Context = Context;
176 Status = XhcPeiCreateTransferTrb (Xhc, Urb);
179 FreePool (Urb);
180 Urb = NULL;
183 return Urb;
187 Free an allocated URB.
190 @param Urb The URB to free.
196 IN URB *Urb
199 if ((Xhc == NULL) || (Urb == NULL)) {
203 FreePool (Urb);
210 @param Urb The urb used to construct the transfer TRB.
218 IN URB *Urb
231 SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
236 Urb->Finished = FALSE;
237 Urb->StartDone = FALSE;
238 Urb->EndDone = FALSE;
239 Urb->Completed = 0;
240 Urb->Result = EFI_USB_NOERROR;
242 Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
244 Urb->Ring = EPRing;
252 Urb->DataPhy = Urb->Data;
258 Urb->TrbStart = EPRing->RingEnqueue;
265 TrbStart->TrbCtrSetup.bmRequestType = Urb->Request->RequestType;
266 TrbStart->TrbCtrSetup.bRequest = Urb->Request->Request;
267 TrbStart->TrbCtrSetup.wValue = Urb->Request->Value;
268 TrbStart->TrbCtrSetup.wIndex = Urb->Request->Index;
269 TrbStart->TrbCtrSetup.wLength = Urb->Request->Length;
275 if (Urb->Ep.Direction == EfiUsbDataIn) {
277 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
286 Urb->TrbNum++;
291 if (Urb->DataLen > 0) {
294 TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT (Urb->DataPhy);
295 TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT (Urb->DataPhy);
296 TrbStart->TrbCtrData.Length = (UINT32) Urb->DataLen;
304 if (Urb->Ep.Direction == EfiUsbDataIn) {
306 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
315 Urb->TrbNum++;
327 if (Urb->Ep.Direction == EfiUsbDataIn) {
329 } else if (Urb->Ep.Direction == EfiUsbDataOut) {
342 Urb->TrbNum++;
343 Urb->TrbEnd = (TRB_TEMPLATE *) (UINTN) TrbStart;
353 while (TotalLen < Urb->DataLen) {
354 if ((TotalLen + 0x10000) >= Urb->DataLen) {
355 Len = Urb->DataLen - TotalLen;
360 TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
361 TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
378 Urb->TrbNum = TrbNum;
379 Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;
388 while (TotalLen < Urb->DataLen) {
389 if ((TotalLen + 0x10000) >= Urb->DataLen) {
390 Len = Urb->DataLen - TotalLen;
395 TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
396 TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);
413 Urb->TrbNum = TrbNum;
414 Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;
434 @param Urb The urb which makes the endpoint halted.
443 IN URB *Urb
451 SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
455 Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8) (Urb->Ep.Direction));
471 Status = XhcPeiSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);
493 @param Urb The urb which doesn't get completed in a specified timeout range.
502 IN URB *Urb
510 SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
514 Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8) (Urb->Ep.Direction));
530 Status = XhcPeiSetTrDequeuePointer (Xhc, SlotId, Dci, Urb);
546 Check if the Trb is a transaction of the URB.
549 @param Urb The transfer ring to be checked.
551 @retval TRUE It is a transaction of the URB.
552 @retval FALSE It is not any transaction of the URB.
558 IN URB *Urb
564 CheckedTrb = Urb->Ring->RingSeg0;
566 ASSERT (Urb->Ring->TrbNumber == CMD_RING_TRB_NUMBER || Urb->Ring->TrbNumber == TR_RING_TRB_NUMBER);
568 for (Index = 0; Index < Urb->Ring->TrbNumber; Index++) {
579 Check the URB's execution result and update the URB's
583 @param Urb The URB to check result.
585 @return Whether the result of URB transfer is finialized.
591 IN URB *Urb
599 URB *CheckedUrb;
605 ASSERT ((Xhc != NULL) && (Urb != NULL));
609 if (Urb->Finished) {
616 Urb->Result |= EFI_USB_ERR_SYSTEM;
647 // Update the status of Urb according to the finished event regardless of whether
648 // the urb is current checked one or in the XHCI's async transfer list.
652 if (XhcPeiIsTransferRingTrb (TRBPtr, Urb)) {
653 CheckedUrb = Urb;
745 return Urb->Finished;
749 Execute the transfer by polling the URB. This is a synchronous operation.
752 @param CmdTransfer The executed URB is for cmd transfer or not.
753 @param Urb The URB to execute.
765 IN URB *Urb,
780 SlotId = XhcPeiBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);
784 Dci = XhcPeiEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));
796 Finished = XhcPeiCheckUrbResult (Xhc, Urb);
804 Urb->Result = EFI_USB_ERR_TIMEOUT;
806 } else if (Urb->Result != EFI_USB_NOERROR) {
1531 // remove urb from XHCI's asynchronous transfer list.
1634 // remove urb from XHCI's asynchronous transfer list.
2394 @param Urb The dequeue pointer of the transfer ring specified
2395 by the urb to be updated.
2407 IN URB *Urb
2415 DEBUG ((EFI_D_INFO, "XhcPeiSetTrDequeuePointer: Slot = 0x%x, Dci = 0x%x, Urb = 0x%x\n", SlotId, Dci, Urb));
2421 PhyAddr = UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb->Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER));
2422 CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS;
