Lines Matching refs:UINT8
78 UINT8 Lan : 1; /// 0: Disable; 1: Enable
79 UINT8 Azalia : 2; /// 0: Disable; 1: Enable; 2: Auto
80 UINT8 Sata : 1; /// 0: Disable; 1: Enable
81 UINT8 Smbus : 1; /// 0: Disable; 1: Enable
82 UINT8 LpeEnabled : 2; /// 0: Disabled; 1: PCI Mode 2: ACPI Mode
83 UINT8 Reserved[1]; /// Reserved fields for future expansion w/o protocol change
106 UINT8 Enable : 1; /// 0: Disable; 1: Enable. This would take effect while UsbPerPortCtl is enabled
107 UINT8 Panel : 1; /// 0: Back Panel Port; 1: Front Panel Port.
108 UINT8 Dock : 1; /// 0: Not docking port; 1: Docking Port.
109 UINT8 Rsvdbits : 5;
113 UINT8 Enable : 1; /// 0: Disable; 1: Enable
114 UINT8 Rsvdbits : 7;
118 UINT8 Enable : 2; /// 0: 0: Disabled; 1: PCI Mode 2: ACPI Mode
119 UINT8 Rsvdbits : 6;
134 UINT8 Mode : 2; /// 0: Disable; 1: Enable, 2: Auto, 3: Smart Auto
135 UINT8 PreBootSupport : 1; /// 0: No xHCI driver available; 1: xHCI driver available
136 UINT8 XhciStreams : 1; /// 0: Disable; 1: Enable
137 UINT8 Rsvdbits : 4;
141 UINT8 UsbPerPortCtl : 1; /// 0: Disable; 1: Enable Per-port enable control
142 UINT8 Ehci1Usbr : 1; /// 0: Disable; 1: Enable EHCI 1 USBR
143 UINT8 RsvdBits : 6;
192 UINT8 Enable : 1; /// Root Port enabling, 0: Disable; 1: Enable.
193 UINT8 Hide : 1; /// Whether or not to hide the configuration space of this port
194 UINT8 SlotImplemented : 1;
195 UINT8 HotPlug : 1;
196 UINT8 PmSci : 1;
197 UINT8 ExtSync : 1; /// Extended Synch
198 UINT8 Rsvdbits : 2;
202 UINT8 UnsupportedRequestReport : 1;
203 UINT8 FatalErrorReport : 1;
204 UINT8 NoFatalErrorReport : 1;
205 UINT8 CorrectableErrorReport : 1;
206 UINT8 PmeInterrupt : 1;
207 UINT8 SystemErrorOnFatalError : 1;
208 UINT8 SystemErrorOnNonFatalError : 1;
209 UINT8 SystemErrorOnCorrectableError : 1;
211 UINT8 AdvancedErrorReporting : 1;
212 UINT8 TransmitterHalfSwing : 1;
213 UINT8 Reserved : 6; /// Reserved fields for future expansion w/o protocol change
215 UINT8 FunctionNumber; /// The function number this root port is mapped to.
216 UINT8 PhysicalSlotNumber;
250 UINT8 RevId;
251 UINT8 BaseClassCode;
252 UINT8 SubClassCode;
259 UINT8 RevId; ///< PCI configuration space offset 8; 0xFF means all steppings
308 UINT8 TempRootPortBusNumMin;
309 UINT8 TempRootPortBusNumMax;
312 UINT8 NumOfDevAspmOverride; /// Number of PCI Express card Aspm setting override
314 UINT8 PcieDynamicGating; /// Need PMC enable it first from PMC 0x3_12 MCU 318.
327 UINT8 Enable : 1; /// 0: Disable; 1: Enable
328 UINT8 HotPlug : 1; /// 0: Disable; 1: Enable
329 UINT8 MechSw : 1; /// 0: Disable; 1: Enable
330 UINT8 External : 1; /// 0: Disable; 1: Enable
331 UINT8 SpinUp : 1; /// 0: Disable; 1: Enable the COMRESET initialization Sequence to the device
332 UINT8 Rsvdbits : 3; /// Reserved fields for future expansion w/o protocol change
337 UINT8 RaidAlternateId : 1; /// 0: Disable; 1: Enable
338 UINT8 Raid0 : 1; /// 0: Disable; 1: Enable RAID0
339 UINT8 Raid1 : 1; /// 0: Disable; 1: Enable RAID1
340 UINT8 Raid10 : 1; /// 0: Disable; 1: Enable RAID10
341 UINT8 Raid5 : 1; /// 0: Disable; 1: Enable RAID5
342 UINT8 Irrt : 1; /// 0: Disable; 1: Enable Intel Rapid Recovery Technology
343 UINT8 OromUiBanner : 1; /// 0: Disable; 1: Enable OROM UI and BANNER
344 UINT8 HddUnlock : 1; /// 0: Disable; 1: Indicates that the HDD password unlock in the OS is enabled
346 UINT8 LedLocate : 1; /// 0: Disable; 1: Indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS
347 UINT8 IrrtOnly : 1; /// 0: Disable; 1: Allow only IRRT drives to span internal and external ports
348 UINT8 TestMode : 1; /// 0: Disable; 1: Allow entrance to the PCH SATA test modes
349 UINT8 SalpSupport : 1; /// 0: Disable; 1: Enable Aggressive Link Power Management
350 UINT8 LegacyMode : 1; /// 0: Native PCI mode; 1: Legacy mode, when SATA controller is operating in IDE mode
351 UINT8 SpeedSupport : 4; /// Indicates the maximum speed the SATA controller can support
354 UINT8 Rsvdbits : 7; // Reserved fields for future expansion w/o protocol change
362 UINT8 RevisionId; /// 0xFF applies to all steppings
363 UINT8 FrontPanelSupport;
374 UINT8 Pme : 1; /// 0: Disable; 1: Enable
375 UINT8 DS : 1; /// 0: Docking is not supported; 1:Docking is supported
376 UINT8 DA : 1; /// 0: Docking is not attached; 1:Docking is attached
377 UINT8 HdmiCodec : 1; /// 0: Disable; 1: Enable
378 UINT8 AzaliaVCi : 1; /// 0: Disable; 1: Enable
379 UINT8 Rsvdbits : 3;
380 UINT8 AzaliaVerbTableNum; /// Number of verb tables provided by platform
389 UINT8 NumRsvdSmbusAddresses;
390 UINT8 *RsvdSmbusAddressTable;
397 UINT8 MeWakeSts : 1;
398 UINT8 MeHrstColdSts : 1;
399 UINT8 MeHrstWarmSts : 1;
400 UINT8 MeHostPowerDn : 1;
401 UINT8 WolOvrWkSts : 1;
402 UINT8 Rsvdbits : 3;
406 UINT8 PmeB0S5Dis : 1;
407 UINT8 WolEnableOverride : 1;
408 UINT8 Rsvdbits : 6;
443 UINT8 SlpStrchSusUp : 1; /// Enable/Disable SLP_X Stretching After SUS Well Power Up
444 UINT8 SlpLanLowDc : 1;
445 UINT8 Rsvdbits : 6;
460 UINT8 GlobalSmi : 1;
461 UINT8 BiosInterface : 1;
462 UINT8 RtcLock : 1;
463 UINT8 BiosLock : 1;
464 UINT8 Rsvdbits : 4;
465 UINT8 PchBiosLockSwSmiNumber;
487 UINT8 NumOfDevLtrOverride; /// Number of Pci Express card listed in LTR override table
495 UINT8 LpssPciModeEnabled : 1; /// Determines if LPSS PCI Mode enabled
496 UINT8 Dma0Enabled : 1; /// Determines if LPSS DMA1 enabled
497 UINT8 Dma1Enabled : 1; /// Determines if LPSS DMA2 enabled
498 UINT8 I2C0Enabled : 1; /// Determines if LPSS I2C #1 enabled
499 UINT8 I2C1Enabled : 1; /// Determines if LPSS I2C #2 enabled
500 UINT8 I2C2Enabled : 1; /// Determines if LPSS I2C #3 enabled
501 UINT8 I2C3Enabled : 1; /// Determines if LPSS I2C #4 enabled
502 UINT8 I2C4Enabled : 1; /// Determines if LPSS I2C #5 enabled
503 UINT8 I2C5Enabled : 1; /// Determines if LPSS I2C #6 enabled
504 UINT8 I2C6Enabled : 1; /// Determines if LPSS I2C #7 enabled
505 UINT8 Pwm0Enabled : 1; /// Determines if LPSS PWM #1 enabled
506 UINT8 Pwm1Enabled : 1; /// Determines if LPSS PWM #2 enabled
507 UINT8 Hsuart0Enabled : 1; /// Determines if LPSS HSUART #1 enabled
508 UINT8 Hsuart1Enabled : 1; /// Determines if LPSS HSUART #2 enabled
509 UINT8 SpiEnabled : 1; /// Determines if LPSS SPI enabled
510 UINT8 Rsvdbits : 2;
517 UINT8 eMMCEnabled : 1; /// Determines if SCC eMMC enabled
518 UINT8 SdioEnabled : 1; /// Determines if SCC SDIO enabled
519 UINT8 SdcardEnabled : 1; /// Determines if SCC SD Card enabled
520 UINT8 HsiEnabled : 1; /// Determines if SCC HSI enabled
521 UINT8 eMMC45Enabled : 1; /// Determines if SCC eMMC 4.5 enabled
522 UINT8 eMMC45DDR50Enabled : 1; /// Determines if DDR50 enabled for eMMC 4.5
523 UINT8 eMMC45HS200Enabled : 1; /// Determines if HS200nabled for eMMC 4.5
524 UINT8 Rsvdbits : 1;
525 UINT8 SdCardSDR25Enabled : 1; /// Determines if SDR25 for SD Card
526 UINT8 SdCardDDR50Enabled : 1; /// Determines if DDR50 for SD Card
527 UINT8 Rsvdbits1 : 6;
528 UINT8 eMMC45RetuneTimerValue; /// Determines retune timer value.
535 UINT8 Revision;
536 UINT8 BusNumber; /// PCI Bus Number of the PCH device
551 UINT8 IdleReserve;
552 UINT8 EhciPllCfgEnable;
553 UINT8 AcpiHWRed; //Hardware Reduced Mode
