Lines Matching refs:MCID_Commutable
3216 { 22, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #22 = ADCrr
3220 { 26, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo17,0,nullptr }, // Inst #26 = ADDSrr
3224 { 30, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #30 = ADDrr
3235 { 41, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #41 = ANDrr
3271 { 77, 4, 0, 18, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo42,0,nullptr }, // Inst #77 = CMNzrr
3293 { 99, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #99 = EORrr
3405 { 211, 5, 1, 43, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Select)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x0ULL, nullptr, nullptr, OperandInfo77,0,nullptr }, // Inst #211 = MOVCCr
3432 { 238, 6, 1, 280, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #238 = MUL
3433 { 239, 6, 1, 280, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo93,0,nullptr }, // Inst #239 = MULv5
3440 { 246, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #246 = ORRrr
3555 { 361, 7, 2, 321, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo105,0,nullptr }, // Inst #361 = SMULL
3556 { 362, 7, 2, 282, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #362 = SMULLv5
3665 { 471, 4, 0, 80, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo42,0,nullptr }, // Inst #471 = TEQrr
3672 { 478, 4, 0, 80, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo42,0,nullptr }, // Inst #478 = TSTrr
3690 { 496, 7, 2, 321, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo105,0,nullptr }, // Inst #496 = UMULL
3691 { 497, 7, 2, 282, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #497 = UMULLv5
3729 { 535, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #535 = VABDLsv2i64
3730 { 536, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #536 = VABDLsv4i32
3731 { 537, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #537 = VABDLsv8i16
3732 { 538, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #538 = VABDLuv2i64
3733 { 539, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #539 = VABDLuv4i32
3734 { 540, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #540 = VABDLuv8i16
3735 { 541, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #541 = VABDfd
3736 { 542, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #542 = VABDfq
3737 { 543, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #543 = VABDsv16i8
3738 { 544, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #544 = VABDsv2i32
3739 { 545, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #545 = VABDsv4i16
3740 { 546, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #546 = VABDsv4i32
3741 { 547, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #547 = VABDsv8i16
3742 { 548, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #548 = VABDsv8i8
3743 { 549, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #549 = VABDuv16i8
3744 { 550, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #550 = VABDuv2i32
3745 { 551, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #551 = VABDuv4i16
3746 { 552, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #552 = VABDuv4i32
3747 { 553, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #553 = VABDuv8i16
3748 { 554, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #554 = VABDuv8i8
3764 { 570, 5, 1, 421, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #570 = VADDHNv2i32
3765 { 571, 5, 1, 421, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #571 = VADDHNv4i16
3766 { 572, 5, 1, 421, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #572 = VADDHNv8i8
3767 { 573, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #573 = VADDLsv2i64
3768 { 574, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #574 = VADDLsv4i32
3769 { 575, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #575 = VADDLsv8i16
3770 { 576, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #576 = VADDLuv2i64
3771 { 577, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #577 = VADDLuv4i32
3772 { 578, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #578 = VADDLuv8i16
3780 { 586, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #586 = VADDfd
3781 { 587, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #587 = VADDfq
3782 { 588, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #588 = VADDv16i8
3783 { 589, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #589 = VADDv1i64
3784 { 590, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #590 = VADDv2i32
3785 { 591, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #591 = VADDv2i64
3786 { 592, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #592 = VADDv4i16
3787 { 593, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #593 = VADDv4i32
3788 { 594, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #594 = VADDv8i16
3789 { 595, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #595 = VADDv8i8
3790 { 596, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #596 = VANDd
3791 { 597, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #597 = VANDq
3804 { 610, 5, 1, 406, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #610 = VCEQfd
3805 { 611, 5, 1, 407, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #611 = VCEQfq
3806 { 612, 5, 1, 408, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #612 = VCEQv16i8
3807 { 613, 5, 1, 409, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #613 = VCEQv2i32
3808 { 614, 5, 1, 409, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #614 = VCEQv4i16
3809 { 615, 5, 1, 408, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #615 = VCEQv4i32
3810 { 616, 5, 1, 408, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #616 = VCEQv8i16
3811 { 617, 5, 1, 409, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #617 = VCEQv8i8
3976 { 782, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #782 = VEORd
3977 { 783, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #783 = VEORq
4002 { 808, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #808 = VHADDsv16i8
4003 { 809, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #809 = VHADDsv2i32
4004 { 810, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #810 = VHADDsv4i16
4005 { 811, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #811 = VHADDsv4i32
4006 { 812, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #812 = VHADDsv8i16
4007 { 813, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #813 = VHADDsv8i8
4008 { 814, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #814 = VHADDuv16i8
4009 { 815, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #815 = VHADDuv2i32
4010 { 816, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #816 = VHADDuv4i16
4011 { 817, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #817 = VHADDuv4i32
4012 { 818, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #818 = VHADDuv8i16
4013 { 819, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #819 = VHADDuv8i8
4453 { 1259, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1259 = VMAXfd
4454 { 1260, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1260 = VMAXfq
4455 { 1261, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1261 = VMAXsv16i8
4456 { 1262, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1262 = VMAXsv2i32
4457 { 1263, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1263 = VMAXsv4i16
4458 { 1264, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1264 = VMAXsv4i32
4459 { 1265, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1265 = VMAXsv8i16
4460 { 1266, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1266 = VMAXsv8i8
4461 { 1267, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1267 = VMAXuv16i8
4462 { 1268, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1268 = VMAXuv2i32
4463 { 1269, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1269 = VMAXuv4i16
4464 { 1270, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1270 = VMAXuv4i32
4465 { 1271, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1271 = VMAXuv8i16
4466 { 1272, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1272 = VMAXuv8i8
4471 { 1277, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1277 = VMINfd
4472 { 1278, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1278 = VMINfq
4473 { 1279, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1279 = VMINsv16i8
4474 { 1280, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1280 = VMINsv2i32
4475 { 1281, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1281 = VMINsv4i16
4476 { 1282, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1282 = VMINsv4i32
4477 { 1283, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1283 = VMINsv8i16
4478 { 1284, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1284 = VMINsv8i8
4479 { 1285, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1285 = VMINuv16i8
4480 { 1286, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1286 = VMINuv2i32
4481 { 1287, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1287 = VMINuv4i16
4482 { 1288, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1288 = VMINuv4i32
4483 { 1289, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1289 = VMINuv8i16
4484 { 1290, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1290 = VMINuv8i8
4583 { 1389, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1389 = VMULLp8
4588 { 1394, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1394 = VMULLsv2i64
4589 { 1395, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1395 = VMULLsv4i32
4590 { 1396, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1396 = VMULLsv8i16
4591 { 1397, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1397 = VMULLuv2i64
4592 { 1398, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1398 = VMULLuv4i32
4593 { 1399, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1399 = VMULLuv8i16
4595 { 1401, 5, 1, 455, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1401 = VMULfd
4596 { 1402, 5, 1, 456, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1402 = VMULfq
4597 { 1403, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1403 = VMULpd
4598 { 1404, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1404 = VMULpq
4605 { 1411, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1411 = VMULv16i8
4606 { 1412, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1412 = VMULv2i32
4607 { 1413, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1413 = VMULv4i16
4608 { 1414, 5, 1, 460, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1414 = VMULv4i32
4609 { 1415, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1415 = VMULv8i16
4610 { 1416, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1416 = VMULv8i8
4635 { 1441, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1441 = VORRd
4640 { 1446, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1446 = VORRq
4689 { 1495, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1495 = VQADDsv16i8
4690 { 1496, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1496 = VQADDsv1i64
4691 { 1497, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1497 = VQADDsv2i32
4692 { 1498, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1498 = VQADDsv2i64
4693 { 1499, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1499 = VQADDsv4i16
4694 { 1500, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1500 = VQADDsv4i32
4695 { 1501, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1501 = VQADDsv8i16
4696 { 1502, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1502 = VQADDsv8i8
4697 { 1503, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1503 = VQADDuv16i8
4698 { 1504, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1504 = VQADDuv1i64
4699 { 1505, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1505 = VQADDuv2i32
4700 { 1506, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1506 = VQADDuv2i64
4701 { 1507, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1507 = VQADDuv4i16
4702 { 1508, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1508 = VQADDuv4i32
4703 { 1509, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1509 = VQADDuv8i16
4704 { 1510, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1510 = VQADDuv8i8
4717 { 1523, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1523 = VQDMULHv2i32
4718 { 1524, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1524 = VQDMULHv4i16
4719 { 1525, 5, 1, 460, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1525 = VQDMULHv4i32
4720 { 1526, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1526 = VQDMULHv8i16
4723 { 1529, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1529 = VQDMULLv2i64
4724 { 1530, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo126,0,nullptr }, // Inst #1530 = VQDMULLv4i32
4744 { 1550, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1550 = VQRDMULHv2i32
4745 { 1551, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1551 = VQRDMULHv4i16
4746 { 1552, 5, 1, 460, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1552 = VQRDMULHv4i32
4747 { 1553, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1553 = VQRDMULHv8i16
4838 { 1644, 5, 1, 424, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1644 = VRADDHNv2i32
4839 { 1645, 5, 1, 424, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1645 = VRADDHNv4i16
4840 { 1646, 5, 1, 424, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1646 = VRADDHNv8i8
4845 { 1651, 5, 1, 449, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1651 = VRECPSfd
4846 { 1652, 5, 1, 450, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1652 = VRECPSfq
4859 { 1665, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1665 = VRHADDsv16i8
4860 { 1666, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1666 = VRHADDsv2i32
4861 { 1667, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1667 = VRHADDsv4i16
4862 { 1668, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1668 = VRHADDsv4i32
4863 { 1669, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1669 = VRHADDsv8i16
4864 { 1670, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1670 = VRHADDsv8i8
4865 { 1671, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1671 = VRHADDuv16i8
4866 { 1672, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1672 = VRHADDuv2i32
4867 { 1673, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1673 = VRHADDuv4i16
4868 { 1674, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1674 = VRHADDuv4i32
4869 { 1675, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1675 = VRHADDuv8i16
4870 { 1676, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1676 = VRHADDuv8i8
4936 { 1742, 5, 1, 449, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1742 = VRSQRTSfd
4937 { 1743, 5, 1, 450, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1743 = VRSQRTSfq
5438 { 2244, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2244 = VTSTv16i8
5439 { 2245, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2245 = VTSTv2i32
5440 { 2246, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2246 = VTSTv4i16
5441 { 2247, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2247 = VTSTv4i32
5442 { 2248, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #2248 = VTSTv8i16
5443 { 2249, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #2249 = VTSTv8i8
5479 { 2285, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo269,0,nullptr }, // Inst #2285 = t2ADCrr
5482 { 2288, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo272,0,nullptr }, // Inst #2288 = t2ADDSrr
5486 { 2292, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276,0,nullptr }, // Inst #2292 = t2ADDrr
5490 { 2296, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2296 = t2ANDrr
5529 { 2335, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2335 = t2EORrr
5630 { 2436, 5, 1, 43, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Select)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x0ULL, nullptr, nullptr, OperandInfo302,0,nullptr }, // Inst #2436 = t2MOVCCr
5655 { 2461, 5, 1, 310, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2461 = t2MUL
5664 { 2470, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2470 = t2ORRrr
5750 { 2556, 6, 2, 322, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2556 = t2SMULL
5859 { 2665, 6, 2, 322, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2665 = t2UMULL
5879 { 2685, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, ImplicitList1, nullptr, OperandInfo331,0,nullptr }, // Inst #2685 = tADC
5885 { 2691, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo336,0,nullptr }, // Inst #2691 = tADDrr
5891 { 2697, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2697 = tAND
5915 { 2721, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2721 = tEOR
5945 { 2751, 6, 2, 51, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo356,0,nullptr }, // Inst #2751 = tMUL
5947 { 2753, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2753 = tORR
5979 { 2785, 4, 0, 263, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo345,0,nullptr }, // Inst #2785 = tTST
