Lines Matching refs:MCID_HasOptionalDef
3215 { 21, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #21 = ADCri
3216 { 22, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #22 = ADCrr
3217 { 23, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #23 = ADCrsi
3218 { 24, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo15,0,nullptr }, // Inst #24 = ADCrsr
3223 { 29, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #29 = ADDri
3224 { 30, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #30 = ADDrr
3225 { 31, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #31 = ADDrsi
3226 { 32, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #32 = ADDrsr
3234 { 40, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #40 = ANDri
3235 { 41, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #41 = ANDrr
3236 { 42, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #42 = ANDrsi
3237 { 43, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #43 = ANDrsr
3238 { 44, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #44 = ASRi
3239 { 45, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #45 = ASRr
3245 { 51, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #51 = BICri
3246 { 52, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #52 = BICrr
3247 { 53, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #53 = BICrsi
3248 { 54, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #54 = BICrsr
3292 { 98, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #98 = EORri
3293 { 99, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #99 = EORrr
3294 { 100, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #100 = EORrsi
3295 { 101, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #101 = EORrsr
3391 { 197, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #197 = LSLi
3392 { 198, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #198 = LSLr
3393 { 199, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #199 = LSRi
3394 { 200, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #200 = LSRr
3399 { 205, 7, 1, 279, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo73,0,nullptr }, // Inst #205 = MLA
3400 { 206, 7, 1, 279, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo74,0,nullptr }, // Inst #206 = MLAv5
3414 { 220, 5, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo82,0,nullptr }, // Inst #220 = MOVi
3418 { 224, 5, 1, 48, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo84,0,nullptr }, // Inst #224 = MOVr
3419 { 225, 5, 1, 48, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo85,0,nullptr }, // Inst #225 = MOVr_TC
3420 { 226, 6, 1, 269, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x3501ULL, nullptr, nullptr, OperandInfo86,0,nullptr }, // Inst #226 = MOVsi
3421 { 227, 7, 1, 269, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2281ULL, nullptr, nullptr, OperandInfo87,0,nullptr }, // Inst #227 = MOVsr
3432 { 238, 6, 1, 280, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #238 = MUL
3433 { 239, 6, 1, 280, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo93,0,nullptr }, // Inst #239 = MULv5
3435 { 241, 5, 1, 52, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo82,0,nullptr }, // Inst #241 = MVNi
3436 { 242, 5, 1, 272, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo84,0,nullptr }, // Inst #242 = MVNr
3437 { 243, 6, 1, 54, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x3501ULL, nullptr, nullptr, OperandInfo86,0,nullptr }, // Inst #243 = MVNsi
3438 { 244, 7, 1, 271, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2281ULL, nullptr, nullptr, OperandInfo94,0,nullptr }, // Inst #244 = MVNsr
3439 { 245, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #245 = ORRri
3440 { 246, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #246 = ORRrr
3441 { 247, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #247 = ORRrsi
3442 { 248, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #248 = ORRrsr
3482 { 288, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #288 = RORi
3483 { 289, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #289 = RORr
3485 { 291, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84,0,nullptr }, // Inst #291 = RRXi
3489 { 295, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #295 = RSBri
3490 { 296, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #296 = RSBrr
3491 { 297, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #297 = RSBrsi
3492 { 298, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #298 = RSBrsr
3493 { 299, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #299 = RSCri
3494 { 300, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #300 = RSCrr
3495 { 301, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #301 = RSCrsi
3496 { 302, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo20,0,nullptr }, // Inst #302 = RSCrsr
3500 { 306, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #306 = SBCri
3501 { 307, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #307 = SBCrr
3502 { 308, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #308 = SBCrsi
3503 { 309, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo15,0,nullptr }, // Inst #309 = SBCrsr
3529 { 335, 9, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo102,0,nullptr }, // Inst #335 = SMLAL
3536 { 342, 9, 2, 281, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #342 = SMLALv5
3555 { 361, 7, 2, 321, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo105,0,nullptr }, // Inst #361 = SMULL
3556 { 362, 7, 2, 282, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #362 = SMULLv5
3647 { 453, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo12,0,nullptr }, // Inst #453 = SUBri
3648 { 454, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #454 = SUBrr
3649 { 455, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #455 = SUBrsi
3650 { 456, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo20,0,nullptr }, // Inst #456 = SUBrsr
3688 { 494, 9, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo102,0,nullptr }, // Inst #494 = UMLAL
3689 { 495, 9, 2, 281, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #495 = UMLALv5
3690 { 496, 7, 2, 321, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo105,0,nullptr }, // Inst #496 = UMULL
3691 { 497, 7, 2, 282, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #497 = UMULLv5
5478 { 2284, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo268,0,nullptr }, // Inst #2284 = t2ADCri
5479 { 2285, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo269,0,nullptr }, // Inst #2285 = t2ADCrr
5480 { 2286, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo270,0,nullptr }, // Inst #2286 = t2ADCrs
5484 { 2290, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274,0,nullptr }, // Inst #2290 = t2ADDri
5486 { 2292, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276,0,nullptr }, // Inst #2292 = t2ADDrr
5487 { 2293, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo277,0,nullptr }, // Inst #2293 = t2ADDrs
5489 { 2295, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2295 = t2ANDri
5490 { 2296, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2296 = t2ANDrr
5491 { 2297, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2297 = t2ANDrs
5492 { 2298, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2298 = t2ASRri
5493 { 2299, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2299 = t2ASRrr
5497 { 2303, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2303 = t2BICri
5498 { 2304, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2304 = t2BICrr
5499 { 2305, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2305 = t2BICrs
5528 { 2334, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2334 = t2EORri
5529 { 2335, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2335 = t2EORrr
5530 { 2336, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2336 = t2EORrs
5614 { 2420, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2420 = t2LSLri
5615 { 2421, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2421 = t2LSLrr
5616 { 2422, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2422 = t2LSRri
5617 { 2423, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2423 = t2LSRrr
5637 { 2443, 5, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo307,0,nullptr }, // Inst #2443 = t2MOVi
5641 { 2447, 5, 1, 48, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo308,0,nullptr }, // Inst #2447 = t2MOVr
5657 { 2463, 5, 1, 52, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo307,0,nullptr }, // Inst #2463 = t2MVNi
5658 { 2464, 5, 1, 53, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2464 = t2MVNr
5659 { 2465, 6, 1, 249, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo312,0,nullptr }, // Inst #2465 = t2MVNs
5660 { 2466, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2466 = t2ORNri
5661 { 2467, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2467 = t2ORNrr
5662 { 2468, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2468 = t2ORNrs
5663 { 2469, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2469 = t2ORRri
5664 { 2470, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2470 = t2ORRrr
5665 { 2471, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2471 = t2ORRrs
5697 { 2503, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2503 = t2RORri
5698 { 2504, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2504 = t2RORrr
5699 { 2505, 5, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, ImplicitList1, nullptr, OperandInfo311,0,nullptr }, // Inst #2505 = t2RRX
5702 { 2508, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo268,0,nullptr }, // Inst #2508 = t2RSBri
5703 { 2509, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2509 = t2RSBrr
5704 { 2510, 7, 1, 250, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2510 = t2RSBrs
5708 { 2514, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo268,0,nullptr }, // Inst #2514 = t2SBCri
5709 { 2515, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo269,0,nullptr }, // Inst #2515 = t2SBCrr
5710 { 2516, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo270,0,nullptr }, // Inst #2516 = t2SBCrs
5825 { 2631, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo274,0,nullptr }, // Inst #2631 = t2SUBri
5827 { 2633, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo276,0,nullptr }, // Inst #2633 = t2SUBrr
5828 { 2634, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo277,0,nullptr }, // Inst #2634 = t2SUBrs
5879 { 2685, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, ImplicitList1, nullptr, OperandInfo331,0,nullptr }, // Inst #2685 = tADC
5881 { 2687, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2687 = tADDi3
5882 { 2688, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo333,0,nullptr }, // Inst #2688 = tADDi8
5885 { 2691, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo336,0,nullptr }, // Inst #2691 = tADDrr
5891 { 2697, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2697 = tAND
5892 { 2698, 6, 2, 50, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2698 = tASRri
5893 { 2699, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2699 = tASRrr
5895 { 2701, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2701 = tBIC
5915 { 2721, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2721 = tEOR
5937 { 2743, 6, 2, 50, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2743 = tLSLri
5938 { 2744, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2744 = tLSLrr
5939 { 2745, 6, 2, 50, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2745 = tLSRri
5940 { 2746, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2746 = tLSRrr
5943 { 2749, 5, 2, 41, 2, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo355,0,nullptr }, // Inst #2749 = tMOVi8
5945 { 2751, 6, 2, 51, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo356,0,nullptr }, // Inst #2751 = tMUL
5946 { 2752, 5, 2, 53, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo357,0,nullptr }, // Inst #2752 = tMVN
5947 { 2753, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2753 = tORR
5955 { 2761, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2761 = tROR
5956 { 2762, 5, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo357,0,nullptr }, // Inst #2762 = tRSB
5957 { 2763, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, ImplicitList1, nullptr, OperandInfo331,0,nullptr }, // Inst #2763 = tSBC
5967 { 2773, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2773 = tSUBi3
5968 { 2774, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo333,0,nullptr }, // Inst #2774 = tSUBi8
5969 { 2775, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo336,0,nullptr }, // Inst #2775 = tSUBrr
