Lines Matching refs:MCID_HasPostISelHook
3215 { 21, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #21 = ADCri
3216 { 22, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #22 = ADCrr
3217 { 23, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #23 = ADCrsi
3218 { 24, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo15,0,nullptr }, // Inst #24 = ADCrsr
3219 { 25, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo16,0,nullptr }, // Inst #25 = ADDSri
3220 { 26, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo17,0,nullptr }, // Inst #26 = ADDSrr
3221 { 27, 6, 1, 3, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18,0,nullptr }, // Inst #27 = ADDSrsi
3222 { 28, 7, 1, 5, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19,0,nullptr }, // Inst #28 = ADDSrsr
3486 { 292, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo16,0,nullptr }, // Inst #292 = RSBSri
3487 { 293, 6, 1, 3, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18,0,nullptr }, // Inst #293 = RSBSrsi
3488 { 294, 7, 1, 5, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19,0,nullptr }, // Inst #294 = RSBSrsr
3493 { 299, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #299 = RSCri
3494 { 300, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #300 = RSCrr
3495 { 301, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #301 = RSCrsi
3496 { 302, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo20,0,nullptr }, // Inst #302 = RSCrsr
3500 { 306, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #306 = SBCri
3501 { 307, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #307 = SBCrr
3502 { 308, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #308 = SBCrsi
3503 { 309, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo15,0,nullptr }, // Inst #309 = SBCrsr
3643 { 449, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo16,0,nullptr }, // Inst #449 = SUBSri
3644 { 450, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo17,0,nullptr }, // Inst #450 = SUBSrr
3645 { 451, 6, 1, 3, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18,0,nullptr }, // Inst #451 = SUBSrsi
3646 { 452, 7, 1, 5, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19,0,nullptr }, // Inst #452 = SUBSrsr
5478 { 2284, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo268,0,nullptr }, // Inst #2284 = t2ADCri
5479 { 2285, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo269,0,nullptr }, // Inst #2285 = t2ADCrr
5480 { 2286, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo270,0,nullptr }, // Inst #2286 = t2ADCrs
5481 { 2287, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo271,0,nullptr }, // Inst #2287 = t2ADDSri
5482 { 2288, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo272,0,nullptr }, // Inst #2288 = t2ADDSrr
5483 { 2289, 6, 1, 238, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo273,0,nullptr }, // Inst #2289 = t2ADDSrs
5700 { 2506, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo316,0,nullptr }, // Inst #2506 = t2RSBSri
5701 { 2507, 6, 1, 58, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo317,0,nullptr }, // Inst #2507 = t2RSBSrs
5708 { 2514, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo268,0,nullptr }, // Inst #2514 = t2SBCri
5709 { 2515, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo269,0,nullptr }, // Inst #2515 = t2SBCrr
5710 { 2516, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo270,0,nullptr }, // Inst #2516 = t2SBCrs
5822 { 2628, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo271,0,nullptr }, // Inst #2628 = t2SUBSri
5823 { 2629, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo272,0,nullptr }, // Inst #2629 = t2SUBSrr
5824 { 2630, 6, 1, 238, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo273,0,nullptr }, // Inst #2630 = t2SUBSrs
