Lines Matching refs:Imm
144 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v;
169 static unsigned translateShiftImm(unsigned imm)
172 //assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
173 if (imm == 0)
175 return imm;
703 int32_t imm;
723 imm = (int32_t)MCOperand_getImm(Op);
746 imm += address;
748 if (imm > HEX_THRESHOLD)
749 SStream_concat(O, "#0x%x", imm);
751 SStream_concat(O, "#%u", imm);
755 if (imm >= 0) {
756 if (imm > HEX_THRESHOLD)
757 SStream_concat(O, "#0x%x", imm);
759 SStream_concat(O, "#%u", imm);
761 if (imm < -HEX_THRESHOLD)
762 SStream_concat(O, "#-0x%x", -imm);
764 SStream_concat(O, "#-%u", -imm);
773 if (imm >= 0 && imm <= HEX_THRESHOLD)
774 SStream_concat(O, "#%u", imm);
776 SStream_concat(O, "#0x%x", imm);
783 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].mem.disp = imm;
786 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
831 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
1002 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
1119 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = ImmOffs;
1122 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = -(int)ImmOffs;
1131 unsigned Imm = (unsigned int)MCOperand_getImm(MO);
1132 if ((Imm & 0xff) > HEX_THRESHOLD)
1133 SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), (Imm & 0xff));
1135 SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), (Imm & 0xff));
1138 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm & 0xff;
1160 unsigned Imm = (unsigned int)MCOperand_getImm(MO);
1162 if (((Imm & 0xff) << 2) > HEX_THRESHOLD) {
1163 SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2));
1165 SStream_concat(O, "#%s%u", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2));
1169 int v = (Imm & 256) ? ((Imm & 0xff) << 2) : -((((int)Imm) & 0xff) << 2);
1171 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v;
1297 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = lsb;
1300 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = width;
1351 unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1352 if (Imm == 0)
1354 //assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
1355 if (Imm > HEX_THRESHOLD)
1356 SStream_concat(O, ", lsl #0x%x", Imm);
1358 SStream_concat(O, ", lsl #%u", Imm);
1361 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm;
1367 unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1369 if (Imm == 0)
1370 Imm = 32;
1371 //assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
1372 if (Imm > HEX_THRESHOLD)
1373 SStream_concat(O, ", asr #0x%x", Imm);
1375 SStream_concat(O, ", asr #%u", Imm);
1378 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm;
1642 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
1650 unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1652 SStream_concat(O, "p%u", imm);
1655 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
1662 unsigned imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1664 SStream_concat(O, "c%u", imm);
1667 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = imm;
1681 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
1696 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
1710 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
1725 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
1732 unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
1733 unsigned tmp = Imm == 0 ? 32 : Imm;
1741 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
1846 // REG IMM, SH_OPC - e.g. R5, LSL #3
2028 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
2045 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
2064 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = 0;
2081 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = OffImm;
2150 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = (unsigned int)Val;
2157 unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2158 if (Imm + 1 > HEX_THRESHOLD)
2159 SStream_concat(O, "#0x%x", Imm + 1);
2161 SStream_concat(O, "#%u", Imm + 1);
2164 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = Imm + 1;
2171 unsigned Imm = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
2172 if (Imm == 0)
2175 switch (Imm) {
2183 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count - 1].shift.value = Imm * 8;
2198 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
2214 MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = tmp;
