Lines Matching refs:info
81 static int radeon_get_pitch_align(struct radeon_info *info, int bpe, uint32_t tiling)
85 if (info->chip_family >= CHIP_FAMILY_R600) {
88 pitch_align = (((info->group_bytes / 8) / bpe) *
89 info->num_banks) * 8;
91 pitch_align = MAX(info->num_banks * 8, pitch_align);
94 pitch_align = MAX(8, (info->group_bytes / (8 * bpe)));
96 pitch_align = MAX(info->group_bytes / bpe, pitch_align);
98 if (info->have_tiling_info)
100 pitch_align = MAX(64, info->group_bytes / bpe);
122 static int radeon_get_height_align(struct radeon_info *info, uint32_t tiling)
126 if (info->chip_family >= CHIP_FAMILY_R600) {
128 height_align = info->num_channels * 8;
145 static int radeon_get_base_align(struct radeon_info *info,
148 int pixel_align = radeon_get_pitch_align(info, bpe, tiling);
149 int height_align = radeon_get_height_align(info, tiling);
152 if (info->chip_family >= CHIP_FAMILY_R600) {
154 base_align = MAX(info->num_banks * info->num_channels * 8 * 8 * bpe,
157 if (info->have_tiling_info)
158 base_align = info->group_bytes;
171 static uint32_t radeon_get_tiling(struct radeon_info *info,
176 if ((handle->usage & sw) && !info->allow_color_tiling)
179 if (info->chip_family >= CHIP_FAMILY_R600)
185 static struct radeon_bo *radeon_alloc(struct radeon_info *info,
200 tiling = radeon_get_tiling(info, handle);
210 radeon_get_pitch_align(info, cpp, tiling));
212 radeon_get_height_align(info, tiling));
222 base_align = radeon_get_base_align(info, cpp, tiling);
224 rbo = radeon_bo_open(info->bufmgr, 0, size, base_align, domain, 0);
246 static void radeon_zero(struct radeon_info *info,
259 struct radeon_info *info = (struct radeon_info *) drv;
267 rbuf->rbo = radeon_bo_open(info->bufmgr,
277 rbuf->rbo = radeon_alloc(info, handle);
284 radeon_zero(info, rbuf->rbo);
325 struct radeon_info *info = (struct radeon_info *) drv;
327 radeon_bo_manager_gem_dtor(info->bufmgr);
328 free(info);
331 static int radeon_init_tile_config(struct radeon_info *info)
340 ret = drmCommandWriteRead(info->fd, DRM_RADEON_INFO,
345 info->tile_config = val;
347 if (info->chip_family >= CHIP_FAMILY_CEDAR) {
348 switch (info->tile_config & 0xf) {
350 info->num_channels = 1;
353 info->num_channels = 2;
356 info->num_channels = 4;
359 info->num_channels = 8;
366 switch ((info->tile_config & 0xf0) >> 4) {
368 info->num_banks = 4;
371 info->num_banks = 8;
374 info->num_banks = 16;
381 switch ((info->tile_config & 0xf00) >> 8) {
383 info->group_bytes = 256;
386 info->group_bytes = 512;
394 switch ((info->tile_config & 0xe) >> 1) {
396 info->num_channels = 1;
399 info->num_channels = 2;
402 info->num_channels = 4;
405 info->num_channels = 8;
412 switch ((info->tile_config & 0x30) >> 4) {
414 info->num_banks = 4;
417 info->num_banks = 8;
424 switch ((info->tile_config & 0xc0) >> 6) {
426 info->group_bytes = 256;
429 info->group_bytes = 512;
437 info->have_tiling_info = 1;
442 static int radeon_probe(struct radeon_info *info)
451 kinfo.value = (long) &info->chipset;
452 err = drmCommandWriteRead(info->fd, DRM_RADEON_INFO, &kinfo, sizeof(kinfo));
461 if (info->chipset == card->pci_device_id) {
462 info->chip_family = card->chip_family;
463 info->is_mobility = card->mobility;
464 info->is_igp = card->igp;
469 if (info->chip_family == CHIP_FAMILY_UNKNOW) {
470 ALOGE("unknown device id 0x%04x", info->chipset);
474 if (info->chip_family >= CHIP_FAMILY_R600) {
475 err = radeon_init_tile_config(info);
482 info->have_tiling_info = 0;
486 info->allow_color_tiling = 0;
489 err = drmCommandWriteRead(info->fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo));
491 ALOGE("failed to get gem info");
495 info->vram_size = mminfo.vram_visible;
496 info->gart_size = mminfo.gart_size;
499 info->chipset, info->chip_family,
500 info->vram_size / 1024 / 1024,
501 info->gart_size / 1024 / 1024);
508 struct radeon_info *info;
510 info = calloc(1, sizeof(*info));
511 if (!info)
514 info->fd = fd;
515 if (radeon_probe(info)) {
516 free(info);
520 info->bufmgr = radeon_bo_manager_gem_ctor(info->fd);
521 if (!info->bufmgr) {
523 free(info);
527 info->base.destroy = drm_gem_radeon_destroy;
528 info->base.alloc = drm_gem_radeon_alloc;
529 info->base.free = drm_gem_radeon_free;
530 info->base.map = drm_gem_radeon_map;
531 info->base.unmap = drm_gem_radeon_unmap;
533 return &info->base;
