Lines Matching full:info
102 struct drm_amdgpu_info_hw_ip *info)
107 request.return_pointer = (uintptr_t)info;
108 request.return_size = sizeof(*info);
152 dev->info.asic_id = dev->dev_info.device_id;
153 dev->info.chip_rev = dev->dev_info.chip_rev;
154 dev->info.chip_external_rev = dev->dev_info.external_rev;
155 dev->info.family_id = dev->dev_info.family;
156 dev->info.max_engine_clk = dev->dev_info.max_engine_clock;
157 dev->info.max_memory_clk = dev->dev_info.max_memory_clock;
158 dev->info.gpu_counter_freq = dev->dev_info.gpu_counter_freq;
159 dev->info.enabled_rb_pipes_mask = dev->dev_info.enabled_rb_pipes_mask;
160 dev->info.rb_pipes = dev->dev_info.num_rb_pipes;
161 dev->info.ids_flags = dev->dev_info.ids_flags;
162 dev->info.num_hw_gfx_contexts = dev->dev_info.num_hw_gfx_contexts;
163 dev->info.num_shader_engines = dev->dev_info.num_shader_engines;
164 dev->info.num_shader_arrays_per_engine =
166 dev->info.vram_type = dev->dev_info.vram_type;
167 dev->info.vram_bit_width = dev->dev_info.vram_bit_width;
168 dev->info.ce_ram_size = dev->dev_info.ce_ram_size;
169 dev->info.vce_harvest_config = dev->dev_info.vce_harvest_config;
170 dev->info.pci_rev_id = dev->dev_info.pci_rev;
172 for (i = 0; i < (int)dev->info.num_shader_engines; i++) {
178 &dev->info.backend_disable[i]);
182 dev->info.backend_disable[i] =
183 (dev->info.backend_disable[i] >> 16) & 0xff;
186 &dev->info.pa_sc_raster_cfg[i]);
190 if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
192 &dev->info.pa_sc_raster_cfg1[i]);
199 dev->info.gb_tile_mode);
203 if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
205 dev->info.gb_macro_tile_mode);
211 &dev->info.gb_addr_cfg);
216 &dev->info.mc_arb_ramcfg);
220 dev->info.cu_active_number = dev->dev_info.cu_active_number;
221 dev->info.cu_ao_mask = dev->dev_info.cu_ao_mask;
222 memcpy(&dev->info.cu_bitmap[0][0], &dev->dev_info.cu_bitmap[0][0], sizeof(dev->info.cu_bitmap));
224 /* TODO: info->max_quad_shader_pipes is not set */
225 /* TODO: info->avail_quad_shader_pipes is not set */
226 /* TODO: info->cache_entries_per_quad_pipe is not set */
231 struct amdgpu_gpu_info *info)
233 if ((dev == NULL) || (info == NULL))
235 /* Get ASIC info*/
236 *info = dev->info;
244 struct amdgpu_heap_info *info)
259 info->heap_size = vram_gtt_info.vram_cpu_accessible_size;
261 info->heap_size = vram_gtt_info.vram_size;
263 info->max_allocation = vram_gtt_info.vram_cpu_accessible_size;
267 sizeof(info->heap_usage),
268 &info->heap_usage);
271 sizeof(info->heap_usage),
272 &info->heap_usage);
277 info->heap_size = vram_gtt_info.gtt_size;
278 info->max_allocation = vram_gtt_info.vram_cpu_accessible_size;
281 sizeof(info->heap_usage),
282 &info->heap_usage);
