Lines Matching full:devid
55 #define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM)
56 #define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G)
57 #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
224 #define IS_MOBILE(devid) ((devid) == PCI_CHIP_I855_GM || \
225 (devid) == PCI_CHIP_I915_GM || \
226 (devid) == PCI_CHIP_I945_GM || \
227 (devid) == PCI_CHIP_I945_GME || \
228 (devid) == PCI_CHIP_I965_GM || \
229 (devid) == PCI_CHIP_I965_GME || \
230 (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
231 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
232 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
234 #define IS_G45(devid) ((devid) == PCI_CHIP_IGD_E_G || \
235 (devid) == PCI_CHIP_Q45_G || \
236 (devid) == PCI_CHIP_G45_G || \
237 (devid) == PCI_CHIP_G41_G)
238 #define IS_GM45(devid) ((devid) == PCI_CHIP_GM45_GM)
239 #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
241 #define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G)
242 #define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G)
244 #define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \
245 (devid) == PCI_CHIP_E7221_G || \
246 (devid) == PCI_CHIP_I915_GM)
248 #define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \
249 (devid) == PCI_CHIP_I945_GME)
251 #define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \
252 (devid) == PCI_CHIP_I945_GM || \
253 (devid) == PCI_CHIP_I945_GME || \
254 IS_G33(devid))
256 #define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \
257 (devid) == PCI_CHIP_Q33_G || \
258 (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
260 #define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \
261 (devid) == PCI_CHIP_845_G || \
262 (devid) == PCI_CHIP_I855_GM || \
263 (devid) == PCI_CHIP_I865_G)
265 #define IS_GEN3(devid) (IS_945(devid) || IS_915(devid))
267 #define IS_GEN4(devid) ((devid) == PCI_CHIP_I965_G || \
268 (devid) == PCI_CHIP_I965_Q || \
269 (devid) == PCI_CHIP_I965_G_1 || \
270 (devid) == PCI_CHIP_I965_GM || \
271 (devid) == PCI_CHIP_I965_GME || \
272 (devid) == PCI_CHIP_I946_GZ || \
273 IS_G4X(devid))
275 #define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
277 #define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
278 (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
279 (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
280 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
281 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
282 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
283 (devid) == PCI_CHIP_SANDYBRIDGE_S)
285 #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
286 IS_HASWELL(devid) || \
287 IS_VALLEYVIEW(devid))
289 #define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
290 (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
291 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
292 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
293 (devid) == PCI_CHIP_IVYBRIDGE_S || \
294 (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
296 #define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \
297 (devid) == PCI_CHIP_VALLEYVIEW_1 || \
298 (devid) == PCI_CHIP_VALLEYVIEW_2 || \
299 (devid) == PCI_CHIP_VALLEYVIEW_3)
301 #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
302 (devid) == PCI_CHIP_HASWELL_M_GT1 || \
303 (devid) == PCI_CHIP_HASWELL_S_GT1 || \
304 (devid) == PCI_CHIP_HASWELL_B_GT1 || \
305 (devid) == PCI_CHIP_HASWELL_E_GT1 || \
306 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
307 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
308 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
309 (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
310 (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
311 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
312 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
313 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
314 (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
315 (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
316 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
317 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
318 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
319 (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
320 (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
321 #define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \
322 (devid) == PCI_CHIP_HASWELL_M_GT2 || \
323 (devid) == PCI_CHIP_HASWELL_S_GT2 || \
324 (devid) == PCI_CHIP_HASWELL_B_GT2 || \
325 (devid) == PCI_CHIP_HASWELL_E_GT2 || \
326 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
327 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
328 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
329 (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
330 (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
331 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
332 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
333 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
334 (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
335 (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
336 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
337 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
338 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
339 (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
340 (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
341 #define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \
342 (devid) == PCI_CHIP_HASWELL_M_GT3 || \
343 (devid) == PCI_CHIP_HASWELL_S_GT3 || \
344 (devid) == PCI_CHIP_HASWELL_B_GT3 || \
345 (devid) == PCI_CHIP_HASWELL_E_GT3 || \
346 (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
347 (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
348 (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
349 (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
350 (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
351 (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
352 (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
353 (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
354 (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
355 (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
356 (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
357 (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
358 (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
359 (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
360 (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
362 #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
363 IS_HSW_GT2(devid) || \
364 IS_HSW_GT3(devid))
366 #define IS_BROADWELL(devid) (((devid & 0xff00) != 0x1600) ? 0 : \
367 (((devid & 0x00f0) >> 4) > 3) ? 0 : \
368 ((devid & 0x000f) == BDW_SPARE) ? 1 : \
369 ((devid & 0x000f) == BDW_ULT) ? 1 : \
370 ((devid & 0x000f) == BDW_IRIS) ? 1 : \
371 ((devid & 0x000f) == BDW_SERVER) ? 1 : \
372 ((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \
373 ((devid & 0x000f) == BDW_ULX) ? 1 : 0)
375 #define IS_CHERRYVIEW(devid) ((devid) == PCI_CHIP_CHERRYVIEW_0 || \
376 (devid) == PCI_CHIP_CHERRYVIEW_1 || \
377 (devid) == PCI_CHIP_CHERRYVIEW_2 || \
378 (devid) == PCI_CHIP_CHERRYVIEW_3)
380 #define IS_GEN8(devid) (IS_BROADWELL(devid) || \
381 IS_CHERRYVIEW(devid))
383 #define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
384 (devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
385 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1 || \
386 (devid) == PCI_CHIP_SKYLAKE_H_GT1 || \
387 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1)
389 #define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \
390 (devid) == PCI_CHIP_SKYLAKE_FUSED0_GT2 || \
391 (devid) == PCI_CHIP_SKYLAKE_FUSED1_GT2 || \
392 (devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \
393 (devid) == PCI_CHIP_SKYLAKE_FUSED2_GT2 || \
394 (devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \
395 (devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \
396 (devid) == PCI_CHIP_SKYLAKE_WKS_GT2 || \
397 (devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \
398 (devid) == PCI_CHIP_SKYLAKE_MOBILE_GT2)
400 #define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3_0 || \
401 (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_1 || \
402 (devid) == PCI_CHIP_SKYLAKE_ULT_GT3_2 || \
403 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \
404 (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
406 #define IS_SKL_GT4(devid) ((devid) == PCI_CHIP_SKYLAKE_SRV_GT4 || \
407 (devid) == PCI_CHIP_SKYLAKE_DT_GT4 || \
408 (devid) == PCI_CHIP_SKYLAKE_SRV_GT4X || \
409 (devid) == PCI_CHIP_SKYLAKE_H_GT4 || \
410 (devid) == PCI_CHIP_SKYLAKE_WKS_GT4)
412 #define IS_KBL_GT1(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT1_5 || \
413 (devid) == PCI_CHIP_KABYLAKE_ULX_GT1_5 || \
414 (devid) == PCI_CHIP_KABYLAKE_DT_GT1_5 || \
415 (devid
416 (devid) == PCI_CHIP_KABYLAKE_ULX_GT1 || \
417 (devid) == PCI_CHIP_KABYLAKE_DT_GT1 || \
418 (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_0 || \
419 (devid) == PCI_CHIP_KABYLAKE_HALO_GT1_1 || \
420 (devid) == PCI_CHIP_KABYLAKE_SRV_GT1)
422 #define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \
423 (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \
424 (devid) == PCI_CHIP_KABYLAKE_ULX_GT2 || \
425 (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \
426 (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \
427 (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \
428 (devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
430 #define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \
431 (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \
432 (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_2)
434 #define IS_KBL_GT4(devid) ((devid) == PCI_CHIP_KABYLAKE_HALO_GT4)
436 #define IS_KABYLAKE(devid) (IS_KBL_GT1(devid) || \
437 IS_KBL_GT2(devid) || \
438 IS_KBL_GT3(devid) || \
439 IS_KBL_GT4(devid))
441 #define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \
442 IS_SKL_GT2(devid) || \
443 IS_SKL_GT3(devid) || \
444 IS_SKL_GT4(devid))
446 #define IS_BROXTON(devid) ((devid) == PCI_CHIP_BROXTON_0 || \
447 (devid) == PCI_CHIP_BROXTON_1 || \
448 (devid) == PCI_CHIP_BROXTON_2 || \
449 (devid) == PCI_CHIP_BROXTON_3 || \
450 (devid) == PCI_CHIP_BROXTON_4)
452 #define IS_GEMINILAKE(devid) ((devid) == PCI_CHIP_GLK || \
453 (devid) == PCI_CHIP_GLK_2X6)
455 #define IS_GEN9(devid) (IS_SKYLAKE(devid) || \
456 IS_BROXTON(devid) || \
457 IS_KABYLAKE(devid) || \
458 IS_GEMINILAKE(devid))
