Lines Matching full:sleb128
93 DW_OP_consts = 0x11, // SLEB128 constant
188 DW_OP_breg0 = 0x70, // base register 0 + SLEB128 offset
189 DW_OP_breg1 = 0x71, // base register 1 + SLEB128 offset
190 DW_OP_breg2 = 0x72, // base register 2 + SLEB128 offset
191 DW_OP_breg3 = 0x73, // base register 3 + SLEB128 offset
192 DW_OP_breg4 = 0x74, // base register 4 + SLEB128 offset
193 DW_OP_breg5 = 0x75, // base register 5 + SLEB128 offset
194 DW_OP_breg6 = 0x76, // base register 6 + SLEB128 offset
195 DW_OP_breg7 = 0x77, // base register 7 + SLEB128 offset
196 DW_OP_breg8 = 0x78, // base register 8 + SLEB128 offset
197 DW_OP_breg9 = 0x79, // base register 9 + SLEB128 offset
198 DW_OP_breg10 = 0x7A, // base register 10 + SLEB128 offset
199 DW_OP_breg11 = 0x7B, // base register 11 + SLEB128 offset
200 DW_OP_breg12 = 0x7C, // base register 12 + SLEB128 offset
201 DW_OP_breg13 = 0x7D, // base register 13 + SLEB128 offset
202 DW_OP_breg14 = 0x7E, // base register 14 + SLEB128 offset
203 DW_OP_breg15 = 0x7F, // base register 15 + SLEB128 offset
204 DW_OP_breg16 = 0x80, // base register 16 + SLEB128 offset
205 DW_OP_breg17 = 0x81, // base register 17 + SLEB128 offset
206 DW_OP_breg18 = 0x82, // base register 18 + SLEB128 offset
207 DW_OP_breg19 = 0x83, // base register 19 + SLEB128 offset
208 DW_OP_breg20 = 0x84, // base register 20 + SLEB128 offset
209 DW_OP_breg21 = 0x85, // base register 21 + SLEB128 offset
210 DW_OP_breg22 = 0x86, // base register 22 + SLEB128 offset
211 DW_OP_breg23 = 0x87, // base register 23 + SLEB128 offset
212 DW_OP_breg24 = 0x88, // base register 24 + SLEB128 offset
213 DW_OP_breg25 = 0x89, // base register 25 + SLEB128 offset
214 DW_OP_breg26 = 0x8A, // base register 26 + SLEB128 offset
215 DW_OP_breg27 = 0x8B, // base register 27 + SLEB128 offset
216 DW_OP_breg28 = 0x8C, // base register 28 + SLEB128 offset
217 DW_OP_breg29 = 0x8D, // base register 29 + SLEB128 offset
218 DW_OP_breg30 = 0x8E, // base register 30 + SLEB128 offset
219 DW_OP_breg31 = 0x8F, // base register 31 + SLEB128 offset
221 DW_OP_fbreg = 0x91, // SLEB128 offset
222 DW_OP_bregx = 0x92, // ULEB128 register followed by SLEB128 offset
