Lines Matching refs:v4i32
29 #define LD_SW(...) LD_W(v4i32, __VA_ARGS__)
40 #define ST_SW(...) ST_W(v4i32, __VA_ARGS__)
433 out0_m = __msa_copy_u_w((v4i32)in0, idx0); \
434 out1_m = __msa_copy_u_w((v4i32)in0, idx1); \
435 out2_m = __msa_copy_u_w((v4i32)in1, idx2); \
436 out3_m = __msa_copy_u_w((v4i32)in1, idx3); \
652 #define DOTP_SH4_SW(...) DOTP_SH4(v4i32, __VA_ARGS__)
666 out0 = (RTYPE)__msa_dotp_s_d((v4i32)mult0, (v4i32)cnst0); \
667 out1 = (RTYPE)__msa_dotp_s_d((v4i32)mult1, (v4i32)cnst1); \
708 out0 = (RTYPE)__msa_dpadd_s_w((v4i32)out0, (v8i16)mult0, (v8i16)cnst0); \
709 out1 = (RTYPE)__msa_dpadd_s_w((v4i32)out1, (v8i16)mult1, (v8i16)cnst1); \
711 #define DPADD_SH2_SW(...) DPADD_SH2(v4i32, __VA_ARGS__)
719 #define DPADD_SH4_SW(...) DPADD_SH4(v4i32, __VA_ARGS__)
733 out0 = (RTYPE)__msa_dpadd_s_d((v2i64)out0, (v4i32)mult0, (v4i32)mult0); \
734 out1 = (RTYPE)__msa_dpadd_s_d((v2i64)out1, (v4i32)mult1, (v4i32)mult1); \
772 v4i32 max_m = __msa_ldi_w(255); \
773 v4i32 out_m; \
775 out_m = __msa_maxi_s_w((v4i32)in, 0); \
776 out_m = __msa_min_s_w((v4i32)max_m, (v4i32)out_m); \
792 res0_m = __msa_hadd_s_d((v4i32)in, (v4i32)in); \
795 sum_m = __msa_copy_s_w((v4i32)res0_m, 0); \
816 sum_m = __msa_copy_u_w((v4i32)res0_m, 0); \
863 #define HSUB_UH2_SW(...) HSUB_UH2(v4i32, __VA_ARGS__)
918 out0 = (RTYPE)__msa_ilvev_w((v4i32)in1, (v4i32)in0); \
919 out1 = (RTYPE)__msa_ilvev_w((v4i32)in3, (v4i32)in2); \
975 #define ILVL_H2_SW(...) ILVL_H2(v4i32, __VA_ARGS__)
986 out0 = (RTYPE)__msa_ilvl_w((v4i32)in0, (v4i32)in1); \
987 out1 = (RTYPE)__msa_ilvl_w((v4i32)in2, (v4i32)in3); \
1006 #define ILVR_B2_SW(...) ILVR_B2(v4i32, __VA_ARGS__)
1018 #define ILVR_B4_SW(...) ILVR_B4(v4i32, __VA_ARGS__)
1033 #define ILVR_H2_SW(...) ILVR_H2(v4i32, __VA_ARGS__)
1042 #define ILVR_H4_SW(...) ILVR_H4(v4i32, __VA_ARGS__)
1046 out0 = (RTYPE)__msa_ilvr_w((v4i32)in0, (v4i32)in1); \
1047 out1 = (RTYPE)__msa_ilvr_w((v4i32)in2, (v4i32)in3); \
1099 #define ILVRL_H2_SW(...) ILVRL_H2(v4i32, __VA_ARGS__)
1103 out0 = (RTYPE)__msa_ilvr_w((v4i32)in0, (v4i32)in1); \
1104 out1 = (RTYPE)__msa_ilvl_w((v4i32)in0, (v4i32)in1); \
1108 #define ILVRL_W2_SW(...) ILVRL_W2(v4i32, __VA_ARGS__)
1204 out0 = (RTYPE)__msa_splati_w((v4i32)in, stidx); \
1205 out1 = (RTYPE)__msa_splati_w((v4i32)in, (stidx + 1)); \
1207 #define SPLATI_W2_SW(...) SPLATI_W2(v4i32, __VA_ARGS__)
1225 #define PCKEV_B2_SW(...) PCKEV_B2(v4i32, __VA_ARGS__)
1379 in0 = (RTYPE)__msa_srar_w((v4i32)in0, (v4i32)shift); \
1380 in1 = (RTYPE)__msa_srar_w((v4i32)in1, (v4i32)shift); \
1388 #define SRAR_W4_SW(...) SRAR_W4(v4i32, __VA_ARGS__)
1417 in0 = (RTYPE)__msa_srari_w((v4i32)in0, shift); \
1418 in1 = (RTYPE)__msa_srari_w((v4i32)in1, shift); \
1426 #define SRARI_W4_SW(...) SRARI_W4(v4i32, __VA_ARGS__)
1494 out = (v4i32)__msa_ilvr_h(sign_m, (v8i16)in); \
1628 out0 = (v16u8)__msa_ilvev_w((v4i32)tmp3_m, (v4i32)tmp2_m); \
1629 out4 = (v16u8)__msa_ilvod_w((v4i32)tmp3_m, (v4i32)tmp2_m); \
1633 out2 = (v16u8)__msa_ilvev_w((v4i32)tmp3_m, (v4i32)tmp2_m); \
1634 out6 = (v16u8)__msa_ilvod_w((v4i32)tmp3_m, (v4i32)tmp2_m); \
1637 out1 = (v16u8)__msa_ilvev_w((v4i32)tmp3_m, (v4i32)tmp2_m); \
1638 out5 = (v16u8)__msa_ilvod_w((v4i32)tmp3_m, (v4i32)tmp2_m); \
1644 out3 = (v16u8)__msa_ilvev_w((v4i32)tmp3_m, (v4i32)tmp2_m); \
1645 out7 = (v16u8)__msa_ilvod_w((v4i32)tmp3_m, (v4i32)tmp2_m); \
1685 v4i32 s0_m, s1_m, s2_m, s3_m; \
1690 out0 = (v4i32)__msa_ilvr_d((v2i64)s2_m, (v2i64)s0_m); \
1691 out1 = (v4i32)__msa_ilvl_d((v2i64)s2_m, (v2i64)s0_m); \
1692 out2 = (v4i32)__msa_ilvr_d((v2i64)s3_m, (v2i64)s1_m); \
1693 out3 = (v4i32)__msa_ilvl_d((v2i64)s3_m, (v2i64)s1_m); \
