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Lines Matching defs:OrigReg

89   bool isSpillCandBB(unsigned OrigReg, VNInfo &OrigVNI, MachineBasicBlock &BB,
104   void runHoistSpills(unsigned OrigReg, VNInfo &OrigVNI,
1078 /// i.e., there should be a living sibling of OrigReg at the insert point.
1080 bool HoistSpillHelper::isSpillCandBB(unsigned OrigReg, VNInfo &OrigVNI,
1083   LiveInterval &OrigLI = LIS.getInterval(OrigReg);
1089   SmallSetVector<unsigned, 16> &Siblings = Virt2SiblingsMap[OrigReg];
1090   assert((LIS.getInterval(OrigReg)).getVNInfoAt(Idx) == &OrigVNI &&
1153   // to the OrigReg. It means the def instruction should dominate all the spills
1229     unsigned OrigReg, VNInfo &OrigVNI, SmallPtrSet<MachineInstr *, 16> &Spills,
1304     if (!isSpillCandBB(OrigReg, OrigVNI, *Block, LiveReg))
1384     unsigned OrigReg = SlotToOrigReg[Slot];
1385     LiveInterval &OrigLI = LIS.getInterval(OrigReg);
1404     runHoistSpills(OrigReg, *OrigVNI, EqValSpills, SpillsToRm, SpillsToIns);