Lines Matching defs:Def
146 /// \brief Track Def -> Use info used for rewriting copies.
278 /// follows the use-def chain to find successive suitable sources.
280 /// def = COPY src.
285 /// def = COPY v2.sub0
287 /// Using a ValueTracker for def = COPY v2.sub0 will give the following
290 /// Then, def can be rewritten into def = COPY v0.
293 /// The current point into the use-def chain.
294 const MachineInstr *Def;
295 /// The index of the definition in Def.
354 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg),
357 Def = MRI.getVRegDef(Reg);
373 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg),
375 assert(DefIdx < Def->getDesc().getNumDefs() &&
376 Def->getOperand(DefIdx).isReg() && "Invalid definition");
377 Reg = Def->getOperand(DefIdx).getReg();
380 /// \brief Following the use-def chain, get the next available source
502 // Both will be live out of the def MBB anyway. Don't extend live range of
608 /// retrieve all Def -> Use along the way up to the next source. Any found
644 // Follow the chain of copies until we reach the top of the use-def chain
650 // Insert the Def -> Use entry for the recently found source.
694 // one use-def which cannot be rewritten.
711 /// from its edges. By inserting a new PHI, we provide a rewritten PHI def
812 /// \brief Given a \p Def.Reg and Def.SubReg pair, use \p RewriteMap to find
814 /// multiple sources for a given \p Def are found along the way, we found a
820 TargetInstrInfo::RegSubRegPair Def,
824 TargetInstrInfo::RegSubRegPair LookupSrc(Def.Reg, Def.SubReg);
853 // Build the new PHI node and return its def register as the new source.
867 /// \brief Rewrite the source found through \p Def, by using the \p RewriteMap
873 RewriteSource(TargetInstrInfo::RegSubRegPair Def,
895 /// \brief Get the next rewritable def source (TrackReg, TrackSubReg)
922 /// \brief Rewrite the source found through \p Def, by using the \p RewriteMap
928 RewriteSource(TargetInstrInfo::RegSubRegPair Def,
930 assert(!TargetRegisterInfo::isPhysicalRegister(Def.Reg) &&
935 getNewSource(&MRI, &TII, Def, RewriteMap);
938 const TargetRegisterClass *DefRC = MRI.getRegClass(Def.Reg);
946 NewCopy->getOperand(0).setSubReg(Def.SubReg);
947 if (Def.SubReg)
953 MRI.replaceRegWith(Def.Reg, NewVR);
1271 TargetInstrInfo::RegSubRegPair Def(CopyDefReg, CopyDefSubReg);
1272 if (!findNextSource(Def.Reg, Def.SubReg, RewriteMap))
1275 RewritePairs.push_back(Def);
1279 for (const auto &Def : RewritePairs) {
1281 MachineInstr *NewCopy = CpyRewriter->RewriteSource(Def, RewriteMap);
1336 /// and only if the def and use are in the same BB.
1540 const auto &Def = NAPhysToVirtMIs.find(Reg);
1541 if (Def != NAPhysToVirtMIs.end()) {
1546 NAPhysToVirtMIs.erase(Def);
1552 unsigned Def = RegMI.first;
1553 if (MachineOperand::clobbersPhysReg(RegMask, Def)) {
1556 NAPhysToVirtMIs.erase(Def);
1667 assert(Def->isCopy() && "Invalid definition");
1668 // Copy instruction are supposed to be: Def = Src.
1670 assert(Def->getNumOperands() == 2 && "Invalid number of operands");
1672 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1677 const MachineOperand &Src = Def->getOperand(1);
1682 assert(Def
1685 if (Def->hasUnmodeledSideEffects())
1688 // Bitcasts with more than one def are not supported.
1689 if (Def->getDesc().getNumDefs() != 1)
1691 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
1696 unsigned SrcIdx = Def->getNumOperands();
1699 const MachineOperand &MO = Def->getOperand(OpIdx);
1711 const MachineOperand &Src = Def->getOperand(SrcIdx);
1716 assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
1719 if (Def->getOperand(DefIdx).getSubReg())
1721 // The case we are checking is Def.<subreg> = REG_SEQUENCE.
1725 // Def.sub0 =
1726 // Def.sub1 =
1727 // is a valid SSA representation for Def.sub0 and Def.sub1, but not for
1728 // Def. Thus, it must not be generated.
1730 // Def.sub0 (i.e, not defining the other subregs) and we would
1742 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
1746 // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
1765 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) &&
1768 if (Def->getOperand(DefIdx).getSubReg())
1781 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
1785 // Def = INSERT_SUBREG v0, v1, sub1
1797 const MachineOperand &MODef = Def->getOperand(DefIdx);
1798 // If the result register (Def) and the base register (v0) do not
1813 // we used for Def.
1818 assert((Def->isExtractSubreg() ||
1819 Def->isExtractSubregLike()) && "Invalid definition");
1821 // Def = EXTRACT_SUBREG v0, sub0
1834 if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg))
1847 assert(Def->isSubregToReg() && "Invalid definition");
1849 // Def = SUBREG_TO_REG Imm, v0, sub0
1855 if (DefSubReg != Def->getOperand(3).getImm())
1859 if (Def->getOperand(2).getSubReg())
1862 return ValueTrackerResult(Def->getOperand(2).getReg(),
1863 Def->getOperand(3).getImm());
1868 assert(Def->isPHI() && "Invalid definition");
1873 if (Def->getOperand(0).getSubReg() != DefSubReg)
1877 for (unsigned i = 1, e = Def->getNumOperands(); i < e; i += 2) {
1878 auto &MO = Def->getOperand(i);
1887 assert(Def && "This method needs a valid definition");
1889 assert(((Def->getOperand(DefIdx).isDef() &&
1890 (DefIdx < Def->getDesc().getNumDefs() ||
1891 Def->getDesc().isVariadic())) ||
1892 Def->getOperand(DefIdx).isImplicit()) &&
1894 if (Def->isCopy())
1896 if (Def->isBitcast())
1902 if (Def->isRegSequence() || Def->isRegSequenceLike())
1904 if (Def->isInsertSubreg() || Def->isInsertSubregLike())
1906 if (Def->isExtractSubreg() || Def->isExtractSubregLike())
1908 if (Def->isSubregToReg())
1910 if (Def->isPHI())
1916 // If we reach a point where we cannot move up in the use-def chain,
1918 if (!Def)
1929 // Update the result before moving up in the use-def chain
1931 Res.setInst(Def);
1933 // If we can still move up in the use-def chain, move to the next
1936 Def = MRI.getVRegDef(Reg);
1944 // early by cutting the use-def chain.
1945 Def = nullptr;
