Lines Matching refs:ISD
15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
18 // expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC;
22 // This does not legalize vector manipulations like ISD::BUILD_VECTOR,
202 if (Op.getOpcode() == ISD::LOAD) {
204 ISD::LoadExtType ExtType = LD->getExtensionType();
205 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
230 } else if (Op.getOpcode() == ISD::STORE) {
248 } else if (Op.getOpcode() == ISD::MSCATTER || Op.getOpcode() == ISD::MSTORE)
262 case ISD::ADD:
263 case ISD::SUB:
264 case ISD::MUL:
265 case ISD::SDIV:
266 case ISD::UDIV:
267 case ISD::SREM:
268 case ISD::UREM:
269 case ISD::SDIVREM:
270 case ISD::UDIVREM:
271 case ISD::FADD:
272 case ISD::FSUB:
273 case ISD::FMUL:
274 case ISD::FDIV:
275 case ISD::FREM:
276 case ISD::AND:
277 case ISD::OR:
278 case ISD::XOR:
279 case ISD::SHL:
280 case ISD::SRA:
281 case ISD::SRL:
282 case ISD::ROTL:
283 case ISD::ROTR:
284 case ISD::BSWAP:
285 case ISD::BITREVERSE:
286 case ISD::CTLZ:
287 case ISD::CTTZ:
288 case ISD::CTLZ_ZERO_UNDEF:
289 case ISD::CTTZ_ZERO_UNDEF:
290 case ISD::CTPOP:
291 case ISD::SELECT:
292 case ISD::VSELECT:
293 case ISD::SELECT_CC:
294 case ISD::SETCC:
295 case ISD::ZERO_EXTEND:
296 case ISD::ANY_EXTEND:
297 case ISD::TRUNCATE:
298 case ISD::SIGN_EXTEND:
299 case ISD::FP_TO_SINT:
300 case ISD::FP_TO_UINT:
301 case ISD::FNEG:
302 case ISD::FABS:
303 case ISD::FMINNUM:
304 case ISD::FMAXNUM:
305 case ISD::FMINNAN:
306 case ISD::FMAXNAN:
307 case ISD::FCOPYSIGN:
308 case ISD::FSQRT:
309 case ISD::FSIN:
310 case ISD::FCOS:
311 case ISD::FPOWI:
312 case ISD::FPOW:
313 case ISD::FLOG:
314 case ISD::FLOG2:
315 case ISD::FLOG10:
316 case ISD::FEXP:
317 case ISD::FEXP2:
318 case ISD::FCEIL:
319 case ISD::FTRUNC:
320 case ISD::FRINT:
321 case ISD::FNEARBYINT:
322 case ISD::FROUND:
323 case ISD::FFLOOR:
324 case ISD::FP_ROUND:
325 case ISD::FP_EXTEND:
326 case ISD::FMA:
327 case ISD::SIGN_EXTEND_INREG:
328 case ISD::ANY_EXTEND_VECTOR_INREG:
329 case ISD::SIGN_EXTEND_VECTOR_INREG:
330 case ISD::ZERO_EXTEND_VECTOR_INREG:
331 case ISD::SMIN:
332 case ISD::SMAX:
333 case ISD::UMIN:
334 case ISD::UMAX:
337 case ISD::FP_ROUND_INREG:
340 case ISD::SINT_TO_FP:
341 case ISD::UINT_TO_FP:
344 case ISD::MSCATTER:
347 case ISD::MSTORE:
387 case ISD::SINT_TO_FP:
388 case ISD::UINT_TO_FP:
391 case ISD::FP_TO_UINT:
392 case ISD::FP_TO_SINT:
394 return PromoteFP_TO_INT(Op, Op->getOpcode() == ISD::FP_TO_SINT);
399 // same overall length. For example, x86 promotes ISD::AND v2i32 to v1i64.
401 // floats. For example, AArch64 promotes ISD::FADD on v4f16 to v4f32.
416 Operands[j] = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op.getOperand(j));
418 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j));
427 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl));
429 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
452 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND :
453 ISD::SIGN_EXTEND;
478 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewVT)) {
479 NewOpc = ISD::FP_TO_SINT;
482 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewVT)) {
483 NewOpc = ISD::FP_TO_UINT;
490 return DAG.getNode(ISD::TRUNCATE, SDLoc(Op), VT, promoted);
513 ISD::LoadExtType ExtType = LD->getExtensionType();
550 ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl, WideVT, Chain, BasePTR,
560 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR,
582 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
583 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask);
594 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
595 Hi = DAG.getNode(ISD::AND, dl, WideVT, Hi, SrcEltBitMask);
600 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi);
604 case ISD::EXTLOAD:
607 case ISD::ZEXTLOAD:
610 case ISD::SEXTLOAD:
614 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
615 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
622 NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
623 Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
679 case ISD::SIGN_EXTEND_INREG:
681 case ISD::ANY_EXTEND_VECTOR_INREG:
683 case ISD::SIGN_EXTEND_VECTOR_INREG:
685 case ISD::ZERO_EXTEND_VECTOR_INREG:
687 case ISD::BSWAP:
689 case ISD::VSELECT:
691 case ISD::SELECT:
693 case ISD::UINT_TO_FP:
695 case ISD::FNEG:
697 case ISD::SETCC:
699 case ISD::BITREVERSE:
701 case ISD::CTLZ_ZERO_UNDEF:
702 case ISD::CTTZ_ZERO_UNDEF:
730 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
731 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
732 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
733 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand)
749 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, Ops);
754 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1);
755 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2);
759 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes);
761 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask);
762 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask);
763 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2);
764 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
771 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Expand ||
772 TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Expand)
783 Op = DAG.getNode(ISD::SHL, DL, VT, Op, ShiftSz);
784 return DAG.getNode(ISD::SRA, DL, VT, Op, ShiftSz);
808 ISD::BITCAST, DL, VT,
828 return DAG.getNode(ISD::SRA, DL, VT,
829 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
859 return DAG.getNode(ISD::BITCAST, DL, VT,
883 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
885 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
892 if (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, VT.getScalarType()))
905 (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, ByteVT) ||
906 (TLI.isOperationLegalOrCustom(ISD::SHL, ByteVT) &&
907 TLI.isOperationLegalOrCustom(ISD::SRL, ByteVT) &&
908 TLI.isOperationLegalOrCustomOrPromote(ISD::AND, ByteVT) &&
909 TLI.isOperationLegalOrCustomOrPromote(ISD::OR, ByteVT)))) {
911 Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Op.getOperand(0));
914 Op = DAG.getNode(ISD::BITREVERSE, DL, ByteVT, Op);
915 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
921 if (!TLI.isOperationLegalOrCustom(ISD::SHL, VT) ||
922 !TLI.isOperationLegalOrCustom(ISD::SRL, VT) ||
923 !TLI.isOperationLegalOrCustomOrPromote(ISD::AND, VT) ||
924 !TLI.isOperationLegalOrCustomOrPromote(ISD::OR, VT))
949 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
950 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
951 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand ||
965 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1);
966 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
970 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes);
972 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask);
973 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
974 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
975 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val);
983 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
984 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
1004 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord);
1005 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask);
1010 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI);
1011 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW);
1012 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO);
1015 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO);
1020 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) {
1024 return DAG.getNode(ISD::FSUB, DL, Op.getValueType(),
1032 unsigned Opc = Op.getOpcode() == ISD::CTLZ_ZERO_UNDEF ? ISD::CTLZ : ISD::CTTZ;
1052 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS,
1055 ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS,
1057 Ops[i] = DAG.getNode(ISD::SETCC, dl,
1066 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
