Lines Matching refs:RegisterVT
287 MVT RegisterVT;
291 NumIntermediates, RegisterVT);
294 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
295 assert(RegisterVT.getSizeInBits() ==
573 MVT RegisterVT;
577 NumIntermediates, RegisterVT);
582 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!");
628 MVT RegisterVT = TLI.getRegisterType(Context, ValueVT);
631 RegVTs.push_back(RegisterVT);
657 MVT RegisterVT = RegVTs[Value];
663 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT);
665 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag);
675 !RegisterVT.isInteger() || RegisterVT.isVector())
683 unsigned RegSize = RegisterVT.getSizeInBits();
691 Parts[i] = DAG.getConstant(0, dl, RegisterVT);
729 RegisterVT, P, DAG.getValueType(FromVT));
733 NumRegs, RegisterVT, ValueVT, V);
758 MVT RegisterVT = RegVTs[Value];
760 if (ExtendKind == ISD::ANY_EXTEND && TLI.isZExtFree(Val, RegisterVT))
764 &Parts[Part], NumParts, RegisterVT, V, ExtendKind);
828 MVT RegisterVT = RegVTs[Value];
832 Ops.push_back(DAG.getRegister(TheReg, RegisterVT));
7533 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7537 MyFlags.VT = RegisterVT;
7758 MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), VT);
7762 NumRegs, RegisterVT, VT, nullptr,
7846 MVT RegisterVT = TLI->getRegisterType(*DAG.getContext(), ValueVTs[0]);
7847 ISD::InputArg RetArg(Flags, RegisterVT, ValueVTs[0], true,
7919 MVT RegisterVT = TLI->getRegisterType(*CurDAG->getContext(), VT);
7922 ISD::InputArg MyFlags(Flags, RegisterVT, VT, isArgValueUsed,
7923 Idx-1, PartBase+i*RegisterVT.getStoreSize());
