Lines Matching defs:Add
199 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
238 // Custom lower Add/Sub/Mul with overflow.
464 // Vector add and sub nodes may conceal a high-half opportunity.
465 // Also, try to fold ADD into CSINC/CSINV..
466 setTargetDAGCombine(ISD::ADD);
1653 // (i64 add 0, (i64 mul (i64 sext|zext i32 %a), (i64 sext|zext i32 %b))
1657 SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Mul,
1663 Value = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Add);
1670 SDValue UpperBits = DAG.getNode(ISD::SRL, DL, MVT::i64, Add,
2191 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2202 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2669 DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getConstant(8, DL, PtrVT));
2698 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
2881 // Add a chain value for each stack argument corresponding
2912 /// and add input and output parameter nodes.
3113 PtrOff = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
3130 DstAddr = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, PtrOff);
3222 // Add argument registers to the end of the list so that they are known live
3228 // Add a register mask operand representing the call-preserved registers.
3347 // Add the flag if we have it.
3387 // Use ADRP/ADD or ADRP/LDR for everything else: the small model on ELF and
3425 /// change the first "ldr" instruction to an appropriate "add x0, x0, #imm" for
3477 /// add x0, x0, #:tlsdesc_lo12:var
3511 // FIXME: add -mtls-size command line option and make it control the 16MiB
3600 return DAG.getNode(ISD::ADD, DL, PtrVT, ThreadBase, TPOff);
3634 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
4084 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
4172 // Use ADRP/ADD or ADRP/LDR for everything else: the small memory model on
4247 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(8, DL, PtrVT));
4250 GRTop = DAG.getNode(ISD::ADD, DL, PtrVT, GRTop,
4261 VRTopAddr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4265 VRTop = DAG.getNode(ISD::ADD, DL, PtrVT, VRTop,
4274 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(24, DL, PtrVT));
4282 DAG.getNode(ISD::ADD, DL, PtrVT, VAList, DAG.getConstant(28, DL, PtrVT));
4331 VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4353 SDValue VANext = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
4418 DAG.getNode(ISD::ADD, DL, VT, FrameAddr, Offset),
4604 // I - Constant that can be used with an ADD instruction
4753 /// vector. If it is invalid, don't add anything to Ops.
4795 // The I constraint applies only to simple ADD or SUB immediate operands:
4797 // The J constraint applies only to ADD or SUB immediates that would be
4798 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
4969 // Add this element source to the list if it's not already there.
7019 // addressing mode or an arithmetic operation: add, sub, and cmp.
7278 // Same encoding for add/sub, just flip the sign.
7284 // immediates is the same as for an add or a sub.
7460 // Check pattern of XOR(ADD(X,Y), Y) where Y is SRA(X, size(X)-1)
7463 N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
7512 // Add (N0 < 0) ? Pow2 - 1 : 0;
7515 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
7516 SDValue CSel = DAG.getNode(AArch64ISD::CSEL, DL, VT, Add, N0, CCVal, Cmp);
7520 Created->push_back(Add.getNode());
7545 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
7554 // (mul x, 2^N + 1) => (add (shl x, N), x)
7560 return DAG.getNode(ISD::ADD, DL, VT, ShiftedVal,
7582 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
7588 SDValue Add =
7589 DAG.getNode(ISD::ADD, DL, VT, ShiftedVal, N->getOperand(0));
7590 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Add);
8312 // (add x, [zext] (setcc cc ...) )
8314 // (csel x, (add x, 1), !cc ...)
8318 assert(Op && Op->getOpcode() == ISD::ADD && "Unexpected operation!");
8352 LHS = DAG.getNode(ISD::ADD, dl, VT, RHS, DAG.getConstant(1, dl, VT));
8356 // The basic add/sub long vector instructions have variants with "2" on the end
8360 // (add (zeroext (extract_high LHS)),
8375 if (N->getOpcode() == ISD::ADD)
8735 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8802 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
8848 if (User->getOpcode() != ISD::ADD
8852 // Check that the add is independent of the load. Otherwise, folding it
8856 // Also check that add is not used in the vector operand. This would also
8967 // Try to swap the 1st and 2nd operand as add and min/max instructions
8983 // %cur = add %1, %0
8985 // %pre = add %cur, %shuffle
9014 case ISD::ADD:
9156 /// Target-specific DAG combine for the across vector add reduction.
9158 /// add reduction produced by the LoopVectorizer. It is the log2-shuffle
9162 /// %2 = add %0, %1
9164 /// %4 = add %2, %3
9177 // Check if the input vector is fed by the ADD.
9178 if (N0->getOpcode() != ISD::ADD)
9197 return tryMatchAcrossLaneShuffleForReduction(N, N0, ISD::ADD, DAG);
9215 if (User->getOpcode() != ISD::ADD ||
9219 // Check that the add is independent of the load/store. Otherwise, folding
9387 // | ADD | |0xff| | |
9447 // equivalent to zero extending the add and displacing it by half the integer
9548 ADD)
9638 // Do not add new nodes to DAG combiner worklist.
9849 case ISD::ADD:
9989 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
9999 IsInc = (Op->getOpcode() == ISD::ADD);
10118 ReplaceReductionResults(N, Results, DAG, ISD::ADD, AArch64ISD::SADDV);
10121 ReplaceReductionResults(N, Results, DAG, ISD::ADD, AArch64ISD::UADDV);
