Lines Matching full:next
8 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1
9 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
10 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
20 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #8
21 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
22 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
32 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #16
33 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
34 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
44 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, lsl #24
45 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
46 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
56 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].8h, #1
57 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
58 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
68 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].8h, #1, lsl #8
69 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
70 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
80 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, msl #8
81 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
82 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
92 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #1, msl #16
93 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
94 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
104 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].16b, #1
105 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
106 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
116 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].2d, #0x00ffff0000ffff
117 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
118 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
128 ; CHECK-NEXT: fmov v[[REG2:[0-9]+]].4s, #3.00000000
129 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
130 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
140 ; CHECK-NEXT: fmov v[[REG2:[0-9]+]].2d, #0.17968750
141 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
142 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
152 ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1
153 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
154 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
164 ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, lsl #8
165 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
166 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
176 ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, lsl #16
177 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
178 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
188 ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, lsl #24
189 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
190 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
200 ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].8h, #1
201 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
202 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
212 ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].8h, #1, lsl #8
213 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
214 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
224 ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, msl #8
225 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
226 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
236 ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #1, msl #16
237 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
238 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
248 ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #1
249 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
259 ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #1, lsl #8
260 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
270 ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #1, lsl #16
271 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
281 ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #1, lsl #24
282 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
292 ; CHECK-NEXT: bic v[[REG2:[0-9]+]].8h, #1
293 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
303 ; CHECK-NEXT: bic v[[REG2:[0-9]+]].8h, #1, lsl #8
304 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
314 ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #1
315 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
325 ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #1, lsl #8
326 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
336 ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #1, lsl #16
337 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
347 ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #1, lsl #24
348 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
358 ; CHECK-NEXT: orr v[[REG2:[0-9]+]].8h, #1
359 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
369 ; CHECK-NEXT: orr v[[REG2:[0-9]+]].8h, #1, lsl #8
370 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
389 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
390 ; CHECK-NEXT: bl f_v8i8
393 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
394 ; CHECK-NEXT: bl f_v4i16
397 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
398 ; CHECK-NEXT: bl f_v2i32
401 ; CHECK-NEXT: bl f_v1i64
404 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
405 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
406 ; CHECK-NEXT: bl f_v16i8
409 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
410 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
411 ; CHECK-NEXT: bl f_v8i16
414 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
415 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
416 ; CHECK-NEXT: bl f_v4i32
419 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
420 ; CHECK-NEXT: bl f_v2i64
429 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
430 ; CHECK-NEXT: bl f_v8i8
433 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
434 ; CHECK-NEXT: bl f_v4i16
437 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
438 ; CHECK-NEXT: bl f_v2i32
441 ; CHECK-NEXT: bl f_v1i64
444 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
445 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
446 ; CHECK-NEXT: bl f_v16i8
449 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
450 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
451 ; CHECK-NEXT: bl f_v8i16
454 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
455 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
456 ; CHECK-NEXT: bl f_v4i32
459 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
460 ; CHECK-NEXT: bl f_v2i64
469 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
470 ; CHECK-NEXT: bl f_v8i8
473 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
474 ; CHECK-NEXT: bl f_v4i16
477 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
478 ; CHECK-NEXT: bl f_v2i32
481 ; CHECK-NEXT: bl f_v1i64
484 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
485 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
486 ; CHECK-NEXT: bl f_v16i8
489 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
490 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
491 ; CHECK-NEXT: bl f_v8i16
494 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
495 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
496 ; CHECK-NEXT: bl f_v4i32
499 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
500 ; CHECK-NEXT: bl f_v2i64
509 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
510 ; CHECK-NEXT: bl f_v8i8
513 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
514 ; CHECK-NEXT: bl f_v4i16
517 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
518 ; CHECK-NEXT: bl f_v2i32
521 ; CHECK-NEXT: bl f_v1i64
524 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
525 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
526 ; CHECK-NEXT: bl f_v16i8
529 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
530 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
531 ; CHECK-NEXT: bl f_v8i16
534 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
535 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
536 ; CHECK-NEXT: bl f_v4i32
539 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
540 ; CHECK-NEXT: bl f_v2i64
549 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
550 ; CHECK-NEXT: bl f_v8i8
553 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
554 ; CHECK-NEXT: bl f_v4i16
557 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
558 ; CHECK-NEXT: bl f_v2i32
561 ; CHECK-NEXT: bl f_v1i64
564 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
565 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
566 ; CHECK-NEXT: bl f_v16i8
569 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
570 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
571 ; CHECK-NEXT: bl f_v8i16
574 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
575 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
576 ; CHECK-NEXT: bl f_v4i32
579 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
580 ; CHECK-NEXT: bl f_v2i64
589 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
590 ; CHECK-NEXT: bl f_v8i8
593 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
594 ; CHECK-NEXT: bl f_v4i16
597 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
598 ; CHECK-NEXT: bl f_v2i32
601 ; CHECK-NEXT: bl f_v1i64
604 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
605 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
606 ; CHECK-NEXT: bl f_v16i8
609 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
610 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
611 ; CHECK-NEXT: bl f_v8i16
614 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
615 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
616 ; CHECK-NEXT: bl f_v4i32
619 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
620 ; CHECK-NEXT: bl f_v2i64
629 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
630 ; CHECK-NEXT: bl f_v8i8
633 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
634 ; CHECK-NEXT: bl f_v4i16
637 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
638 ; CHECK-NEXT: bl f_v2i32
641 ; CHECK-NEXT: bl f_v1i64
644 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
645 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
646 ; CHECK-NEXT: bl f_v16i8
649 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
650 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
651 ; CHECK-NEXT: bl f_v8i16
654 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
655 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
656 ; CHECK-NEXT: bl f_v4i32
659 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
660 ; CHECK-NEXT: bl f_v2i64
669 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
670 ; CHECK-NEXT: bl f_v8i8
673 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
674 ; CHECK-NEXT: bl f_v4i16
677 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
678 ; CHECK-NEXT: bl f_v2i32
681 ; CHECK-NEXT: bl f_v1i64
684 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
685 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
686 ; CHECK-NEXT: bl f_v16i8
689 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
690 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
691 ; CHECK-NEXT: bl f_v8i16
694 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
695 ; CHECK-NEXT
696 ; CHECK-NEXT: bl f_v4i32
699 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
700 ; CHECK-NEXT: bl f_v2i64
709 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
710 ; CHECK-NEXT: bl f_v8i8
713 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
714 ; CHECK-NEXT: bl f_v4i16
717 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
718 ; CHECK-NEXT: bl f_v2i32
721 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
722 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
723 ; CHECK-NEXT: bl f_v16i8
726 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
727 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
728 ; CHECK-NEXT: bl f_v8i16
731 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
732 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
733 ; CHECK-NEXT: bl f_v4i32
742 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
743 ; CHECK-NEXT: bl f_v8i8
746 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
747 ; CHECK-NEXT: bl f_v4i16
750 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
751 ; CHECK-NEXT: bl f_v2i32
754 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
755 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
756 ; CHECK-NEXT: bl f_v16i8
759 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
760 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
761 ; CHECK-NEXT: bl f_v8i16
764 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
765 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
766 ; CHECK-NEXT: bl f_v4i32
775 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
776 ; CHECK-NEXT: bl f_v8i8
779 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
780 ; CHECK-NEXT: bl f_v4i16
783 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
784 ; CHECK-NEXT: bl f_v2i32
787 ; CHECK-NEXT: bl f_v1i64
790 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
791 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
792 ; CHECK-NEXT: bl f_v16i8
795 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
796 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
797 ; CHECK-NEXT: bl f_v8i16
800 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
801 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
802 ; CHECK-NEXT: bl f_v4i32
805 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
806 ; CHECK-NEXT: bl f_v2i64
815 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
816 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
817 ; CHECK-NEXT: bl f_v16i8
820 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
821 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
822 ; CHECK-NEXT: bl f_v8i16
825 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
826 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
827 ; CHECK-NEXT: bl f_v4i32
