Lines Matching full:next
8 ; CHECK-NEXT: ret i32 %A
17 ; CHECK-NEXT: [[B:%.*]] = lshr i32 %A, 3
18 ; CHECK-NEXT: ret i32 [[B]]
27 ; CHECK-NEXT: ret i32 0
36 ; CHECK-NEXT: [[B:%.*]] = sub i32 0, %A
37 ; CHECK-NEXT: ret i32 [[B]]
45 ; CHECK-NEXT: ret i32 0
54 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 %A, 123
55 ; CHECK-NEXT: ret i1 [[TMP1]]
65 ; CHECK-NEXT: [[A_OFF:%.*]] = add i32 %A, -20
66 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[A_OFF]], 10
67 ; CHECK-NEXT: ret i1 [[TMP1]]
77 ; CHECK-NEXT: [[C:%.*]] = icmp ugt i8 %A, -11
78 ; CHECK-NEXT: ret i1 [[C]]
88 ; CHECK-NEXT: [[C:%.*]] = icmp ult i8 %A, -10
89 ; CHECK-NEXT: ret i1 [[C]]
99 ; CHECK-NEXT: [[R_V:%.*]] = select i1 %C, i32 6, i32 3
100 ; CHECK-NEXT: [[R:%.*]] = lshr i32 %X, [[R:%.*]].v
101 ; CHECK-NEXT: ret i32 [[R]]
110 ; CHECK-NEXT: [[B_V:%.*]] = select i1 %C, i32 10, i32 5
111 ; CHECK-NEXT: [[B:%.*]] = lshr i32 %X, [[B:%.*]].v
112 ; CHECK-NEXT: ret i32 [[B]]
122 ; CHECK-NEXT: ret i32 1
130 ; CHECK-NEXT: ret i32 1
138 ; CHECK-NEXT: ret i32 0
148 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 %b, -2
149 ; CHECK-NEXT: [[DIV2:%.*]] = lshr i32 %a, [[TMP1]]
150 ; CHECK-NEXT: ret i32 [[DIV2]]
160 ; CHECK-NEXT: [[DIV:%.*]] = udiv <2 x i64> %x, <i64 192, i64 192>
161 ; CHECK-NEXT: ret <2 x i64> [[DIV]]
170 ; CHECK-NEXT: [[DIV:%.*]] = sdiv <2 x i64> %x, <i64 -3, i64 -4>
171 ; CHECK-NEXT: ret <2 x i64> [[DIV]]
180 ; CHECK-NEXT: [[DIV:%.*]] = sub <2 x i64> zeroinitializer, %x
181 ; CHECK-NEXT: ret <2 x i64> [[DIV]]
189 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 %x, 1
190 ; CHECK-NEXT: [[A:%.*]] = zext i1 [[TMP1]] to i32
191 ; CHECK-NEXT: ret i32 [[A]]
199 ; CHECK-NEXT: [[TMP1:%.*]] = add i32 %x, 1
200 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 3
201 ; CHECK-NEXT: [[A:%.*]] = select i1 [[TMP2]], i32 %x, i32 0
202 ; CHECK-NEXT: ret i32 [[A]]
210 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 %a, 3
211 ; CHECK-NEXT: ret i32 [[DIV]]
220 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 %a, 4
221 ; CHECK-NEXT: ret i32 [[DIV]]
230 ; CHECK-NEXT: [[DIV:%.*]] = udiv i32 %a, 3
231 ; CHECK-NEXT: ret i32 [[DIV]]
240 ; CHECK-NEXT: [[DIV:%.*]] = lshr i32 %a, 2
241 ; CHECK-NEXT: ret i32 [[DIV]]
250 ; CHECK-NEXT: [[DIV:%.*]] = shl nsw i32 %a, 1
251 ; CHECK-NEXT: ret i32 [[DIV]]
260 ; CHECK-NEXT: [[DIV:%.*]] = shl nsw i32 %a, 2
261 ; CHECK-NEXT: ret i32 [[DIV]]
270 ; CHECK-NEXT: [[DIV:%.*]] = shl nuw i32 %a, 1
271 ; CHECK-NEXT: ret i32 [[DIV]]
280 ; CHECK-NEXT: [[DIV:%.*]] = mul nuw i32 %a, 12
281 ; CHECK-NEXT: ret i32 [[DIV]]
290 ; CHECK-NEXT: [[MUL_LOBIT:%.*]] = and i32 %a, 1
291 ; CHECK-NEXT: ret i32 [[MUL_LOBIT]]
300 ; CHECK-NEXT: ret i32 %a
309 ; CHECK-NEXT: ret <2 x i32> zeroinitializer
318 ; CHECK-NEXT: [[SHL:%.*]] = shl i32 2, %b
319 ; CHECK-NEXT: [[DIV:%.*]] = lshr i32 [[SHL]], 2
320 ; CHECK-NEXT: [[DIV2:%.*]] = udiv i32 %a, [[DIV]]
321 ; CHECK-NEXT: ret i32 [[DIV2]]
331 ; CHECK-NEXT: [[DIV:%.*]] = udiv exact <2 x i64> %x, <i64 192, i64 192>
332 ; CHECK-NEXT: ret <2 x i64> [[DIV]]
341 ; CHECK-NEXT: [[DIV:%.*]] = sdiv exact <2 x i64> %x, <i64 -3, i64 -4>
342 ; CHECK-NEXT: ret <2 x i64> [[DIV]]
351 ; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 2147483647
352 ; CHECK-NEXT: [[MUL:%.*]] = udiv exact i32 [[AND]], 2147483647
353 ; CHECK-NEXT: ret i32 [[MUL]]
362 ; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 2147483647
363 ; CHECK-NEXT: [[MUL:%.*]] = lshr exact i32 [[AND]], %A
364 ; CHECK-NEXT: ret i32 [[MUL]]
376 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> %A, <i32 2147483647, i32 2147483647>
377 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw <2 x i32> <i32 1, i32 1>, %A
378 ; CHECK-NEXT: [[MUL:%.*]] = sdiv exact <2 x i32> [[AND]], [[SHL]]
379 ; CHECK-NEXT: ret <2 x i32> [[MUL]]
389 ; CHECK-NEXT: entry:
390 ; CHECK-NEXT: store i32 0, i32* %b, align 4
391 ; CHECK-NEXT: br i1 undef, label %lor.rhs, label %lor.end
393 ; CHECK-NEXT: br label %lor.end
395 ; CHECK-NEXT: ret i32 0
416 ; CHECK-NEXT: [[TMP1:%.*]] = sdiv i8 %x, 127
417 ; CHECK-NEXT: [[DIV:%.*]] = sext i8 [[TMP1]] to i32
418 ; CHECK-NEXT: ret i32 [[DIV]]
429 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 %x, -128
430 ; CHECK-NEXT: [[DIV:%.*]] = zext i1 [[TMP1]] to i32
431 ; CHECK-NEXT: ret i32 [[DIV]]
442 ; CHECK-NEXT: [[TMP1:%.*]] = sdiv <3 x i8> %x, <i8 127, i8 127, i8 127>
443 ; CHECK-NEXT: [[DIV:%.*]] = sext <3 x i8> [[TMP1]] to <3 x i32>
444 ; CHECK-NEXT: ret <3 x i32> [[DIV]]
453 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> %x, <i8 -128, i8 -128>
454 ; CHECK-NEXT: [[DIV:%.*]] = zext <2 x i1> [[TMP1]] to <2 x i32>
455 ; CHECK-NEXT: ret <2 x i32> [[DIV]]
466 ; CHECK-NEXT: [[CONV:%.*]] = sext i8 %x to i32
467 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[CONV]], 128
468 ; CHECK-NEXT: ret i32 [[DIV]]
477 ; CHECK-NEXT: [[CONV:%.*]] = sext i8 %x to i32
478 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[CONV]], -129
479 ; CHECK-NEXT: ret i32 [[DIV]]
490 ; CHECK-NEXT: [[CONV:%.*]] = sext i16 %x to i32
491 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[CONV]], 65535
492 ; CHECK-NEXT: ret i32 [[DIV]]
