Lines Matching full:next
8 ; CHECK-NEXT: ret i32 %A
16 ; CHECK-NEXT: ret i32 -1
24 ; CHECK-NEXT: ret i8 -1
32 ; CHECK-NEXT: ret i1 %A
40 ; CHECK-NEXT: ret i1 true
48 ; CHECK-NEXT: ret i1 %A
56 ; CHECK-NEXT: ret i32 %A
65 ; CHECK-NEXT: ret i32 -1
74 ; CHECK-NEXT: ret i8 -1
84 ; CHECK-NEXT: ret i8 -1
94 ; CHECK-NEXT: ret i8 -2
105 ; CHECK-NEXT: ret i8 -1
118 ; CHECK-NEXT: [[C:%.*]] = and i32 %A, 8
119 ; CHECK-NEXT: ret i32 [[C]]
128 ; CHECK-NEXT: ret i32 8
138 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32 %A, %B
139 ; CHECK-NEXT: ret i1 [[TMP1]]
150 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ule i32 %A, %B
151 ; CHECK-NEXT: ret i1 [[TMP1]]
162 ; CHECK-NEXT: ret i32 %A
174 ; CHECK-NEXT: [[D:%.*]] = and i32 %A, 5
175 ; CHECK-NEXT: ret i32 [[D]]
186 ; CHECK-NEXT: [[A_OFF:%.*]] = add i32 %A, -50
187 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i32 [[A_OFF]], 49
188 ; CHECK-NEXT: ret i1 [[TMP1]]
199 ; CHECK-NEXT: [[TMP1:%.*]] = or i32 %A, 1
200 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 51
201 ; CHECK-NEXT: ret i1 [[TMP2]]
212 ; CHECK-NEXT: ret i32 %x
221 ; CHECK-NEXT: [[TMP_1_MASK1:%.*]] = add i32 %tmp.1, 2
222 ; CHECK-NEXT: ret i32 [[TMP_1_MASK1]]
234 ; CHECK-NEXT: ret i32 %B
244 ; CHECK-NEXT: [[B:%.*]] = lshr i16 %A, 1
245 ; CHECK-NEXT: [[D:%.*]] = xor i16 [[B]], -24575
246 ; CHECK-NEXT: ret i16 [[D]]
258 ; CHECK-NEXT: [[TMP1:%.*]] = fcmp uno double %Y, %X
259 ; CHECK-NEXT: ret i1 [[TMP1]]
270 ; CHECK-NEXT: [[NOTLHS:%.*]] = icmp ne i32 %A, 0
271 ; CHECK-NEXT: [[NOTRHS:%.*]] = icmp ne i32 %B, 57
272 ; CHECK-NEXT: [[F:%.*]] = and i1 [[NOTRHS]], [[NOTLHS]]
273 ; CHECK-NEXT: ret i1 [[F]]
285 ; CHECK-NEXT: [[TMP1:%.*]] = or i32 %A, %B
286 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
287 ; CHECK-NEXT: ret i1 [[TMP2]]
298 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32* %A, null
299 ; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32* %B, null
300 ; CHECK-NEXT: [[E:%.*]] = and i1 [[TMP1]], [[TMP2]]
301 ; CHECK-NEXT: ret i1 [[E]]
313 ; CHECK-NEXT: [[TMP1:%.*]] = or i32 %A, %B
314 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32 [[TMP1]], 0
315 ; CHECK-NEXT: ret i1 [[TMP2]]
326 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i32* %A, null
327 ; CHECK-NEXT: [[TMP2:%.*]] = icmp ne i32* %B, null
328 ; CHECK-NEXT: [[E:%.*]] = or i1 [[TMP1]], [[TMP2]]
329 ; CHECK-NEXT: ret i1 [[E]]
341 ; CHECK-NEXT: [[D:%.*]] = and i32 %A, -58312
342 ; CHECK-NEXT: [[E:%.*]] = or i32 [[D]], 32962
343 ; CHECK-NEXT: ret i32 [[E]]
355 ; CHECK-NEXT: [[E:%.*]] = and i64 %A, 4294908984
356 ; CHECK-NEXT: [[F:%.*]] = or i64 [[E]], 32962
357 ; CHECK-NEXT: ret i64 [[F]]
372 ; CHECK-NEXT: [[OR_I:%.*]] = select <4 x i1> %and.i1352, <4 x i32> %vecinit6.i176, <4 x i32> %vecinit6.i191
373 ; CHECK-NEXT: ret <4 x i32> [[OR_I]]
385 ; CHECK-NEXT: [[B:%.*]] = or i1 %X, %Y
386 ; CHECK-NEXT: ret i1 [[B]]
395 ; CHECK-NEXT: [[B:%.*]] = or i32 %X, %Y
396 ; CHECK-NEXT: ret i32 [[B]]
405 ; CHECK-NEXT: [[TMP1:%.*]] = or i32 %a, %b
406 ; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], 1135
407 ; CHECK-NEXT: ret i32 [[TMP2]]
416 ; CHECK-NEXT: [[X_OFF:%.*]] = add i32 %x, -23
417 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[X_OFF]], 3
418 ; CHECK-NEXT: ret i1 [[TMP1]]
430 ; CHECK-NEXT: [[OR:%.*]] = select i1 %y, i32 -1, i32 %x
431 ; CHECK-NEXT: ret i32 [[OR]]
440 ; CHECK-NEXT: [[OR:%.*]] = select i1 %y, i32 -1, i32 %x
441 ; CHECK-NEXT: ret i32 [[OR]]
450 ; CHECK-NEXT: [[SEXT:%.*]] = sext i1 %y to i32
451 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SEXT]], %x
452 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SEXT]], [[OR]]
453 ; CHECK-NEXT: ret i32 [[ADD]]
463 ; CHECK-NEXT: [[OR:%.*]] = select <2 x i1> %y, <2 x i32> <i32 -1, i32 -1>, <2 x i32> %x
464 ; CHECK-NEXT: ret <2 x i32> [[OR]]
473 ; CHECK-NEXT: [[OR:%.*]] = select <2 x i1> %y, <2 x i132> <i132 -1, i132 -1>, <2 x i132> %x
474 ; CHECK-NEXT: ret <2 x i132> [[OR]]
483 ; CHECK-NEXT: [[OR:%.*]] = or i32 %a, %b
484 ; CHECK-NEXT: ret i32 [[OR]]
494 ; CHECK-NEXT: [[TMP1:%.*]] = xor i32 %a, -1
495 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[TMP1]], %b
496 ; CHECK-NEXT: ret i32 [[OR]]
506 ; CHECK-NEXT: [[TMP1:%.*]] = xor i32 %a, -1
507 ; CHECK-NEXT: [[OR:%.*]] = xor i32 [[TMP1]], %b
508 ; CHECK-NEXT: ret i32 [[OR]]
519 ; CHECK-NEXT: [[TMP1:%.*]] = xor i32 %a, -1
520 ; CHECK-NEXT: [[OR:%.*]] = xor i32 [[TMP1]], %b
521 ; CHECK-NEXT: ret i32 [[OR]]
532 ; CHECK-NEXT: [[OR:%.*]] = xor i32 %a, %b
533 ; CHECK-NEXT: ret i32 [[OR]]
544 ; CHECK-NEXT: [[OR:%.*]] = xor i32 %a, %b
545 ; CHECK-NEXT: ret i32 [[OR]]
556 ; CHECK-NEXT: [[TMP1:%.*]] = and i32 %x, %z
557 ; CHECK-NEXT: [[OR1:%.*]] = or i32 [[TMP1]], %y
558 ; CHECK-NEXT: ret i32 [[OR1]]
568 ; CHECK-NEXT: [[TMP1:%.*]] = and i8 %c, -33
569 ; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], -65
570 ; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i8 [[TMP2]], 26
571 ; CHECK-NEXT: ret i1 [[TMP3]]
583 ; CHECK-NEXT: [[TMP1:%.*]] = and i8 %c, -33
584 ; CHECK-NEXT: [[TMP2:%.*]] = add i8 [[TMP1]], -65
585 ; CHECK-NEXT: [[TMP3:%.*]] = icmp ult i8 [[TMP2]], 27
586 ; CHECK-NEXT: ret i1 [[TMP3]]
598 ; CHECK-NEXT: ret i1 true
