Lines Matching refs:Processor
41 // Each processor has a SchedClassDesc table with an entry for each SchedClass.
222 // Gather and sort processor information
224 Records.getAllDerivedDefinitions("Processor");
227 // Begin processor table
232 // For each processor
234 // Next processor
235 Record *Processor = ProcessorList[i];
237 const std::string &Name = Processor->getValueAsString("Name");
239 Processor->getValueAsListOfDefs("Features");
244 << "\"Select the " << Name << " processor\", ";
262 // End processor table
363 // Multiple processor models may share an itinerary record. Emit it once.
424 // If this processor defines no itineraries, then leave the itinerary list
526 // EmitProcessorData - Generate data for processor itineraries that were
528 // Itineraries for each processor. The Itinerary lists are indexed on
535 // Multiple processor models may share an itinerary record. Emit it once.
538 // For each processor's machine model
548 // Get processor itinerary name
551 // Get the itinerary list for the processor.
563 // Begin processor itinerary table
580 // End processor itinerary table
587 // value defined in the C++ header. The Record is null if the processor does not
646 // Find the WriteRes Record that defines processor resources for this
652 // specifies a set of processor resources.
667 "defined for processor " + ProcModel.ModelName +
674 // Check this processor's list of write resources.
683 "SchedWrite and its alias on processor " +
689 // TODO: If ProcModel has a base model (previous generation processor),
693 std::string("Processor does not define resources for ")
699 /// Find the ReadAdvance record for the given SchedRead on this processor or
707 // Check this processor's list of aliases for SchedRead.
719 "defined for processor " + ProcModel.ModelName +
726 // Check this processor's ReadAdvanceList.
735 "SchedRead and its alias on processor " +
741 // TODO: If ProcModel has a base model (previous generation processor),
745 std::string("Processor does not define resources for ")
751 // Expand an explicit list of processor resources into a full list of implied
770 PrintFatalError(SubDef->getLoc(), "Processor resource group "
799 // Generate the SchedClass table for this processor and update global
800 // tables. Must be called for each processor in order.
842 // Determine if the SchedClass is actually reachable on this processor. If
843 // not don't try to locate the processor resources, it will fail.
873 // Check this processor's itinerary class resources.
1104 // Emit a SchedClass table for each processor.
1150 // For each processor model.
1152 // Emit processor resource table.
1159 // Begin processor itinerary properties
1181 OS << " " << PM.Index << ", // Processor ID\n";
1202 // Gather and sort processor information
1204 Records.getAllDerivedDefinitions("Processor");
1207 // Begin processor table
1213 // For each processor
1215 // Next processor
1216 Record *Processor = ProcessorList[i];
1218 const std::string &Name = Processor->getValueAsString("Name");
1220 SchedModels.getModelForProc(Processor).ModelName;
1231 // End processor table
1263 // Emit the processor machine model
1265 // Emit the processor lookup data
