Lines Matching refs:ws
116 do_winsys_init(struct radv_amdgpu_winsys *ws, int fd)
131 ws->info.pci_domain = devinfo->businfo.pci->domain;
132 ws->info.pci_bus = devinfo->businfo.pci->bus;
133 ws->info.pci_dev = devinfo->businfo.pci->dev;
134 ws->info.pci_func = devinfo->businfo.pci->func;
138 r = amdgpu_query_gpu_info(ws->dev, &ws->amdinfo);
144 r = amdgpu_query_buffer_size_alignment(ws->dev, &alignment_info);
150 r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
156 r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_VRAM,
163 r = amdgpu_query_heap_info(ws->dev, AMDGPU_GEM_DOMAIN_GTT, 0, >t);
169 r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_DMA, 0, &dma);
175 r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
180 ws->info.pci_id = ws->amdinfo.asic_id; /* TODO: is this correct? */
181 ws->info.vce_harvest_config = ws->amdinfo.vce_harvest_config;
183 switch (ws->info.pci_id) {
184 #define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; break;
192 if (ws->info.family >= CHIP_TONGA)
193 ws->info.chip_class = VI;
194 else if (ws->info.family >= CHIP_BONAIRE)
195 ws->info.chip_class = CIK;
196 else if (ws->info.family >= CHIP_TAHITI)
197 ws->info.chip_class = SI;
204 switch (ws->info.family) {
206 ws->family = FAMILY_SI;
207 ws->rev_id = SI_TAHITI_P_A0;
210 ws->family = FAMILY_SI;
211 ws->rev_id = SI_PITCAIRN_PM_A0;
214 ws->family = FAMILY_SI;
215 ws->rev_id = SI_CAPEVERDE_M_A0;
218 ws->family = FAMILY_SI;
219 ws->rev_id = SI_OLAND_M_A0;
222 ws->family = FAMILY_SI;
223 ws->rev_id = SI_HAINAN_V_A0;
226 ws->family = FAMILY_CI;
227 ws->rev_id = CI_BONAIRE_M_A0;
230 ws->family = FAMILY_KV;
231 ws->rev_id = KV_SPECTRE_A0;
234 ws->family = FAMILY_KV;
235 ws->rev_id = KB_KALINDI_A0;
238 ws->family = FAMILY_CI;
239 ws->rev_id = CI_HAWAII_P_A0;
242 ws->family = FAMILY_KV;
243 ws->rev_id = ML_GODAVARI_A0;
246 ws->family = FAMILY_VI;
247 ws->rev_id = VI_TONGA_P_A0;
250 ws->family = FAMILY_VI;
251 ws->rev_id = VI_ICELAND_M_A0;
254 ws->family = FAMILY_CZ;
255 ws->rev_id = CARRIZO_A0;
258 ws->family = FAMILY_CZ;
259 ws->rev_id = STONEY_A0;
262 ws->family = FAMILY_VI;
263 ws->rev_id = VI_FIJI_P_A0;
266 ws->family = FAMILY_VI;
267 ws->rev_id = VI_POLARIS10_P_A0;
270 ws->family = FAMILY_VI;
271 ws->rev_id = VI_POLARIS11_M_A0;
278 ws->addrlib = radv_amdgpu_addr_create(&ws->amdinfo, ws->family, ws->rev_id, ws->info.chip_class);
279 if (!ws->addrlib) {
288 ws->info.name = get_chip_name(ws->info.family);
289 ws->info.gart_size = gtt.heap_size;
290 ws->info.vram_size = vram.heap_size;
291 ws->info.visible_vram_size = visible_vram.heap_size;
293 ws->info.max_shader_clock = ws->amdinfo.max_engine_clk / 1000;
294 ws->info.max_se = ws->amdinfo.num_shader_engines;
295 ws->info.max_sh_per_se = ws->amdinfo.num_shader_arrays_per_engine;
296 ws->info.has_uvd = 0;
297 ws->info.vce_fw_version = 0;
298 ws->info.has_userptr = TRUE;
299 ws->info.num_render_backends = ws->amdinfo.rb_pipes;
300 ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq;
301 ws->info.num_tile_pipes = radv_cik_get_num_tile_pipes(&ws->amdinfo);
302 ws->info.pipe_interleave_bytes = 256 << ((ws->amdinfo.gb_addr_cfg >> 4) & 0x7);
303 ws->info.has_virtual_memory = TRUE;
304 ws->info.sdma_rings = MIN2(util_bitcount(dma.available_rings),
306 ws->info.compute_rings = MIN2(util_bitcount(compute.available_rings),
310 ws->info.num_good_compute_units = 0;
311 for (i = 0; i < ws->info.max_se; i++)
312 for (j = 0; j < ws->info.max_sh_per_se; j++)
313 ws->info.num_good_compute_units +=
314 util_bitcount(ws->amdinfo.cu_bitmap[i][j]);
316 memcpy(ws->info.si_tile_mode_array, ws->amdinfo.gb_tile_mode,
317 sizeof(ws->amdinfo.gb_tile_mode));
318 ws->info.enabled_rb_mask = ws->amdinfo.enabled_rb_pipes_mask;
320 memcpy(ws->info.cik_macrotile_mode_array, ws->amdinfo.gb_macro_tile_mode,
321 sizeof(ws->amdinfo.gb_macro_tile_mode));
323 ws->info.gart_page_size = alignment_info.size_remote;
325 if (ws->info.chip_class == SI)
326 ws->info.gfx_ib_pad_with_type2 = TRUE;
328 ws->use_ib_bos = ws->family >= FAMILY_CI;
342 struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys*)rws;
344 AddrDestroy(ws->addrlib);
345 amdgpu_device_deinitialize(ws->dev);
354 struct radv_amdgpu_winsys *ws;
360 ws = calloc(1, sizeof(struct radv_amdgpu_winsys));
361 if (!ws)
364 ws->dev = dev;
365 ws->info.drm_major = drm_major;
366 ws->info.drm_minor = drm_minor;
367 if (!do_winsys_init(ws, fd))
370 ws->debug_all_bos = getenv("RADV_DEBUG_ALL_BOS") ? true : false;
371 LIST_INITHEAD(&ws->global_bo_list);
372 pthread_mutex_init(&ws->global_bo_list_lock, NULL);
373 ws->base.query_info = radv_amdgpu_winsys_query_info;
374 ws->base.destroy = radv_amdgpu_winsys_destroy;
375 radv_amdgpu_bo_init_functions(ws);
376 radv_amdgpu_cs_init_functions(ws);
377 radv_amdgpu_surface_init_functions(ws);
379 return &ws->base;
382 free(ws);
