Lines Matching refs:pred
59 struct ir3_instruction *pred; /* current p0.x user, if any */
101 debug_assert(ctx->pred == NULL);
102 ctx->pred = instr;
243 * TODO if any instructions use pred register and have other
273 if (writes_pred(instr) && ctx->pred) {
274 debug_assert(ctx->pred != instr);
457 debug_assert(ctx->pred);
459 ir = ctx->pred->block->shader;
468 /* remap remaining instructions using current pred
469 * to new pred:
471 * TODO is there ever a case when pred isn't first
474 if (ssa(predicated->regs[1]) == ctx->pred) {
476 new_pred = ir3_instr_clone(ctx->pred);
477 /* original pred is scheduled, but new one isn't: */
484 /* all remaining predicated remapped to new pred: */
485 ctx->pred = NULL;
497 /* addr/pred writes are per-block: */
499 ctx->pred = NULL;
559 /* clearing current addr/pred can change what is
565 /* the original instr that wrote addr/pred may have
582 debug_assert(ctx->pred);
585 delay -= distance(ctx, ctx->pred, delay);
604 debug_assert(ir3_delayslots(ctx->pred, br, 0) == 6);
