Lines Matching refs:push
90 struct nouveau_pushbuf *push = nv30->base.pushbuf;
92 BEGIN_NV04(push, NV30_3D(VP_UPLOAD_FROM_ID), 1);
93 PUSH_DATA (push, vp->start);
94 BEGIN_NV04(push, NV30_3D(VP_UPLOAD_INST(0)), 4);
95 PUSH_DATA (push, 0x401f9c6c); /* mov o[hpos], a[0]; */
96 PUSH_DATA (push, 0x0040000d);
97 PUSH_DATA (push, 0x8106c083);
98 PUSH_DATA (push, 0x6041ff80);
99 BEGIN_NV04(push, NV30_3D(VP_UPLOAD_INST(0)), 4);
100 PUSH_DATA (push, 0x401f9c6c); /* mov o[tex0], a[8]; end; */
101 PUSH_DATA (push, 0x0040080d);
102 PUSH_DATA (push, 0x8106c083);
103 PUSH_DATA (push, 0x6041ff9d);
149 struct nouveau_pushbuf *push = nv30->base.pushbuf;
158 if (nouveau_pushbuf_space(push, 512, 8, 0) ||
159 nouveau_pushbuf_refn (push, refs, ARRAY_SIZE(refs)))
198 BEGIN_NV04(push, NV30_3D(VIEWPORT_HORIZ), 2);
199 PUSH_DATA (push, dst->w << 16);
200 PUSH_DATA (push, dst->h << 16);
201 BEGIN_NV04(push, NV30_3D(RT_HORIZ), 5);
202 PUSH_DATA (push, dst->w << 16);
203 PUSH_DATA (push, dst->h << 16);
204 PUSH_DATA (push, format);
205 PUSH_DATA (push, stride);
206 PUSH_RELOC(push, dst->bo, dst->offset, NOUVEAU_BO_LOW, 0, 0);
207 BEGIN_NV04(push, NV30_3D(RT_ENABLE), 1);
208 PUSH_DATA (push, NV30_3D_RT_ENABLE_COLOR0);
213 BEGIN_NV04(push, NV30_3D(VIEWPORT_TRANSLATE_X), 8);
214 PUSH_DATAf(push, 0.0);
215 PUSH_DATAf(push, 0.0);
216 PUSH_DATAf(push, 0.0);
217 PUSH_DATAf(push, 0.0);
218 PUSH_DATAf(push, 1.0);
219 PUSH_DATAf(push, 1.0);
220 PUSH_DATAf(push, 1.0);
221 PUSH_DATAf(push, 1.0);
222 BEGIN_NV04(push, NV30_3D(DEPTH_RANGE_NEAR), 2);
223 PUSH_DATAf(push, 0.0);
224 PUSH_DATAf(push, 1.0);
229 BEGIN_NV04(push, NV30_3D(COLOR_LOGIC_OP_ENABLE), 1);
230 PUSH_DATA (push, 0);
231 BEGIN_NV04(push, NV30_3D(DITHER_ENABLE), 1);
232 PUSH_DATA (push, 0);
233 BEGIN_NV04(push, NV30_3D(BLEND_FUNC_ENABLE), 1);
234 PUSH_DATA (push, 0);
235 BEGIN_NV04(push, NV30_3D(COLOR_MASK), 1);
236 PUSH_DATA (push, 0x01010101);
241 BEGIN_NV04(push, NV30_3D(DEPTH_WRITE_ENABLE), 2);
242 PUSH_DATA (push, 0);
243 PUSH_DATA (push, 0);
244 BEGIN_NV04(push, NV30_3D(STENCIL_ENABLE(0)), 1);
245 PUSH_DATA (push, 0);
246 BEGIN_NV04(push, NV30_3D(STENCIL_ENABLE(1)), 1);
247 PUSH_DATA (push, 0);
248 BEGIN_NV04(push, NV30_3D(ALPHA_FUNC_ENABLE), 1);
249 PUSH_DATA (push, 0);
254 BEGIN_NV04(push, NV30_3D(SHADE_MODEL), 1);
255 PUSH_DATA (push, NV30_3D_SHADE_MODEL_FLAT);
256 BEGIN_NV04(push, NV30_3D(CULL_FACE_ENABLE), 1);
257 PUSH_DATA (push, 0);
258 BEGIN_NV04(push, NV30_3D(POLYGON_MODE_FRONT), 2);
259 PUSH_DATA (push, NV30_3D_POLYGON_MODE_FRONT_FILL);
260 PUSH_DATA (push, NV30_3D_POLYGON_MODE_BACK_FILL);
261 BEGIN_NV04(push, NV30_3D(POLYGON_OFFSET_FILL_ENABLE), 1);
262 PUSH_DATA (push, 0);
263 BEGIN_NV04(push, NV30_3D(POLYGON_STIPPLE_ENABLE), 1);
264 PUSH_DATA (push, 0);
270 BEGIN_NV04(push, NV30_3D(VP_START_FROM_ID), 1);
271 PUSH_DATA (push, vp->start);
272 BEGIN_NV04(push, NV40_3D(VP_ATTRIB_EN), 2);
273 PUSH_DATA (push, 0x00000101); /* attrib: 0, 8 */
274 PUSH_DATA (push, 0x00004000); /* result: hpos, tex0 */
275 BEGIN_NV04(push, NV30_3D(ENGINE), 1);
276 PUSH_DATA (push, 0x00000103);
277 BEGIN_NV04(push, NV30_3D(VP_CLIP_PLANES_ENABLE), 1);
278 PUSH_DATA (push, 0x00000000);
284 BEGIN_NV04(push, NV30_3D(FP_ACTIVE_PROGRAM), 1);
285 PUSH_RELOC(push, fp->bo, fp->offset, fp->domain |
289 BEGIN_NV04(push, NV30_3D(FP_CONTROL), 1);
290 PUSH_DATA (push, 0x02000000);
307 BEGIN_NV04(push, NV30_3D(TEX_OFFSET(0)), 8);
308 PUSH_RELOC(push, src->bo, src->offset, NOUVEAU_BO_LOW, 0, 0);
309 PUSH_RELOC(push, src->bo, texfmt, NOUVEAU_BO_OR,
311 PUSH_DATA (push, NV30_3D_TEX_WRAP_S_CLAMP_TO_EDGE |
314 PUSH_DATA (push, NV40_3D_TEX_ENABLE_ENABLE);
315 PUSH_DATA (push, texswz);
318 PUSH_DATA (push, NV30_3D_TEX_FILTER_MIN_LINEAR |
322 PUSH_DATA (push, NV30_3D_TEX_FILTER_MIN_NEAREST |
326 PUSH_DATA (push, (src->w << 16) | src->h);
327 PUSH_DATA (push, 0x00000000);
328 BEGIN_NV04(push, NV40_3D(TEX_SIZE1(0)), 1);
329 PUSH_DATA (push, 0x00100000 | src->pitch);
330 BEGIN_NV04(push, SUBC_3D(0x0b40), 1);
331 PUSH_DATA (push, src->d < 2 ? 0x00000001 : 0x00000000);
332 BEGIN_NV04(push, NV40_3D(TEX_CACHE_CTL), 1);
333 PUSH_DATA (push, 1);
339 BEGIN_NV04(push, NV30_3D(SCISSOR_HORIZ), 2);
340 PUSH_DATA (push, (dst->x1 - dst->x0) << 16 | dst->x0);
341 PUSH_DATA (push, (dst->y1 - dst->y0) << 16 | dst->y0);
342 BEGIN_NV04(push, NV30_3D(VERTEX_BEGIN_END), 1);
343 PUSH_DATA (push, NV30_3D_VERTEX_BEGIN_END_QUADS);
344 BEGIN_NV04(push, NV30_3D(VTX_ATTR_3F(8)), 3);
345 PUSH_DATAf(push, src->x0);
346 PUSH_DATAf(push, src->y0);
347 PUSH_DATAf(push, src->z);
348 BEGIN_NV04(push, NV30_3D(VTX_ATTR_2I(0)), 1);
349 PUSH_DATA (push, (dst->y0 << 16) | dst->x0);
350 BEGIN_NV04(push, NV30_3D(VTX_ATTR_3F(8)), 3);
351 PUSH_DATAf(push, src->x1);
352 PUSH_DATAf(push, src->y0);
353 PUSH_DATAf(push, src->z);
354 BEGIN_NV04(push, NV30_3D(VTX_ATTR_2I(0)), 1);
355 PUSH_DATA (push, (dst->y0 << 16) | dst->x1);
356 BEGIN_NV04(push, NV30_3D(VTX_ATTR_3F(8)), 3);
357 PUSH_DATAf(push, src->x1);
358 PUSH_DATAf(push, src->y1);
359 PUSH_DATAf(push, src->z);
360 BEGIN_NV04(push, NV30_3D(VTX_ATTR_2I(0)), 1);
361 PUSH_DATA (push, (dst->y1 << 16) | dst->x1);
362 BEGIN_NV04(push, NV30_3D(VTX_ATTR_3F(8)), 3);
363 PUSH_DATAf(push, src->x0);
364 PUSH_DATAf(push, src->y1);
365 PUSH_DATAf(push, src->z);
366 BEGIN_NV04(push, NV30_3D(VTX_ATTR_2I(0)), 1);
367 PUSH_DATA (push, (dst->y1 << 16) | dst->x0);
368 BEGIN_NV04(push, NV30_3D(VERTEX_BEGIN_END), 1);
369 PUSH_DATA (push, NV30_3D_VERTEX_BEGIN_END_STOP);
401 struct nouveau_pushbuf *push = nv30->base.pushbuf;
406 struct nv04_fifo *fifo = push->channel->data;
434 if (nouveau_pushbuf_space(push, 64, 6, 0) ||
435 nouveau_pushbuf_refn (push, refs, 2))
439 BEGIN_NV04(push, NV04_SF2D(DMA_IMAGE_SOURCE), 2);
440 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart);
441 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart);
442 BEGIN_NV04(push, NV04_SF2D(FORMAT), 4);
443 PUSH_DATA (push, ss_fmt);
444 PUSH_DATA (push, dst->pitch << 16 | dst->pitch);
445 PUSH_RELOC(push, dst->bo, dst->offset, NOUVEAU_BO_LOW, 0, 0);
446 PUSH_RELOC(push, dst->bo, dst->offset, NOUVEAU_BO_LOW, 0, 0);
447 BEGIN_NV04(push, NV05_SIFM(SURFACE), 1);
448 PUSH_DATA (push, nv30->screen->surf2d->handle);
450 BEGIN_NV04(push, NV04_SSWZ(DMA_IMAGE), 1);
451 PUSH_RELOC(push, dst->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart);
452 BEGIN_NV04(push, NV04_SSWZ(FORMAT), 2);
453 PUSH_DATA (push, ss_fmt | (util_logbase2(dst->w) << 16) |
455 PUSH_RELOC(push, dst->bo, dst->offset, NOUVEAU_BO_LOW, 0, 0);
456 BEGIN_NV04(push, NV05_SIFM(SURFACE), 1);
457 PUSH_DATA (push, nv30->screen->swzsurf->handle);
460 BEGIN_NV04(push, NV03_SIFM(DMA_IMAGE), 1);
461 PUSH_RELOC(push, src->bo, 0, NOUVEAU_BO_OR, fifo->vram, fifo->gart);
462 BEGIN_NV04(push, NV03_SIFM(COLOR_FORMAT), 8);
463 PUSH_DATA (push, si_fmt);
464 PUSH_DATA (push, NV03_SIFM_OPERATION_SRCCOPY);
465 PUSH_DATA (push, ( dst->y0 << 16) | dst->x0);
466 PUSH_DATA (push, ((dst->y1 - dst->y0) << 16) | (dst->x1 - dst->x0));
467 PUSH_DATA (push, ( dst->y0 << 16) | dst->x0);
468 PUSH_DATA (push, ((dst->y1 - dst->y0) << 16) | (dst->x1 - dst->x0));
469 PUSH_DATA (push, ((src->x1 - src->x0) << 20) / (dst->x1 - dst->x0));
470 PUSH_DATA (push, ((src->y1 - src->y0) << 20) / (dst->y1 - dst->y0));
471 BEGIN_NV04(push, NV03_SIFM(SIZE), 4);
472 PUSH_DATA (push, align(src->h, 2) << 16 | align(src->w, 2));
473 PUSH_DATA (push, src->pitch | si_arg);
474 PUSH_RELOC(push, src->bo, src->offset, NOUVEAU_BO_LOW, 0, 0);
475 PUSH_DATA (push, (src->y0 << 20) | src->x0 << 4);
498 struct nouveau_pushbuf *push = nv30->base.pushbuf;
503 struct nv04_fifo *fifo = push->channel->data;
512 BEGIN_NV04(push, NV03_M2MF(DMA_BUFFER_IN), 2);
513 PUSH_DATA (push, (src->domain == NOUVEAU_BO_VRAM) ? fifo->vram : fifo->gart);
514 PUSH_DATA (push, (dst->domain == NOUVEAU_BO_VRAM) ? fifo->vram : fifo->gart);
519 if (nouveau_pushbuf_space(push, 32, 2, 0) ||
520 nouveau_pushbuf_refn (push, refs, 2))
523 BEGIN_NV04(push, NV03_M2MF(OFFSET_IN), 8);
524 PUSH_RELOC(push, src->bo, src_offset, NOUVEAU_BO_LOW, 0, 0);
525 PUSH_RELOC(push, dst->bo, dst_offset, NOUVEAU_BO_LOW, 0, 0);
526 PUSH_DATA (push, src->pitch);
527 PUSH_DATA (push, dst->pitch);
528 PUSH_DATA (push, w * src->cpp);
529 PUSH_DATA (push, lines);
530 PUSH_DATA (push, NV03_M2MF_FORMAT_INPUT_INC_1 |
532 PUSH_DATA (push, 0x00000000);
533 BEGIN_NV04(push, NV04_GRAPH(M2MF, NOP), 1);
534 PUSH_DATA (push, 0x00000000);
535 BEGIN_NV04(push, NV03_M2MF(OFFSET_OUT), 1);
536 PUSH_DATA (push, 0x00000000);
697 struct nouveau_pushbuf *push = nv->pushbuf;
703 BEGIN_NV04(push, NV03_M2MF(DMA_BUFFER_IN), 2);
704 PUSH_DATA (push, (s_dom == NOUVEAU_BO_VRAM) ? fifo->vram : fifo->gart);
705 PUSH_DATA (push, (d_dom == NOUVEAU_BO_VRAM) ? fifo->vram : fifo->gart);
711 if (nouveau_pushbuf_space(push, 32, 2, 0) ||
712 nouveau_pushbuf_refn (push, refs, 2))
715 BEGIN_NV04(push, NV03_M2MF(OFFSET_IN), 8);
716 PUSH_RELOC(push, src, s_off, NOUVEAU_BO_LOW, 0, 0);
717 PUSH_RELOC(push, dst, d_off, NOUVEAU_BO_LOW, 0, 0);
718 PUSH_DATA (push, 4096);
719 PUSH_DATA (push, 4096);
720 PUSH_DATA (push, 4096);
721 PUSH_DATA (push, lines);
722 PUSH_DATA (push, NV03_M2MF_FORMAT_INPUT_INC_1 |
724 PUSH_DATA (push, 0x00000000);
725 BEGIN_NV04(push, NV04_GRAPH(M2MF, NOP), 1);
726 PUSH_DATA (push, 0x00000000);
727 BEGIN_NV04(push, NV03_M2MF(OFFSET_OUT), 1);
728 PUSH_DATA (push, 0x00000000);
735 if (nouveau_pushbuf_space(push, 32, 2, 0) ||
736 nouveau_pushbuf_refn (push, refs, 2))
739 BEGIN_NV04(push, NV03_M2MF(OFFSET_IN), 8);
740 PUSH_RELOC(push, src, s_off, NOUVEAU_BO_LOW, 0, 0);
741 PUSH_RELOC(push, dst, d_off, NOUVEAU_BO_LOW, 0, 0);
742 PUSH_DATA (push, size);
743 PUSH_DATA (push, size);
744 PUSH_DATA (push, size);
745 PUSH_DATA (push, 1);
746 PUSH_DATA (push, NV03_M2MF_FORMAT_INPUT_INC_1 |
748 PUSH_DATA (push, 0x00000000);
749 BEGIN_NV04(push, NV04_GRAPH(M2MF, NOP), 1);
750 PUSH_DATA (push, 0x00000000);
751 BEGIN_NV04(push, NV03_M2MF(OFFSET_OUT), 1);
752 PUSH_DATA (push, 0x00000000);
