Lines Matching refs:push
34 struct nouveau_pushbuf *push)
70 BEGIN_NV04(push, SUBC_CP(NV01_SUBCHAN_OBJECT), 1);
71 PUSH_DATA (push, screen->compute->handle);
73 BEGIN_NV04(push, NV50_CP(UNK02A0), 1);
74 PUSH_DATA (push, 1);
75 BEGIN_NV04(push, NV50_CP(DMA_STACK), 1);
76 PUSH_DATA (push, fifo->vram);
77 BEGIN_NV04(push, NV50_CP(STACK_ADDRESS_HIGH), 2);
78 PUSH_DATAh(push, screen->stack_bo->offset);
79 PUSH_DATA (push, screen->stack_bo->offset);
80 BEGIN_NV04(push, NV50_CP(STACK_SIZE_LOG), 1);
81 PUSH_DATA (push, 4);
83 BEGIN_NV04(push, NV50_CP(UNK0290), 1);
84 PUSH_DATA (push, 1);
85 BEGIN_NV04(push, NV50_CP(LANES32_ENABLE), 1);
86 PUSH_DATA (push, 1);
87 BEGIN_NV04(push, NV50_CP(REG_MODE), 1);
88 PUSH_DATA (push, NV50_COMPUTE_REG_MODE_STRIPED);
89 BEGIN_NV04(push, NV50_CP(UNK0384), 1);
90 PUSH_DATA (push, 0x100);
91 BEGIN_NV04(push, NV50_CP(DMA_GLOBAL), 1);
92 PUSH_DATA (push, fifo->vram);
95 BEGIN_NV04(push, NV50_CP(GLOBAL_ADDRESS_HIGH(i)), 2);
96 PUSH_DATA (push, 0);
97 PUSH_DATA (push, 0);
98 BEGIN_NV04(push, NV50_CP(GLOBAL_LIMIT(i)), 1);
99 PUSH_DATA (push, 0);
100 BEGIN_NV04(push, NV50_CP(GLOBAL_MODE(i)), 1);
101 PUSH_DATA (push, NV50_COMPUTE_GLOBAL_MODE_LINEAR);
104 BEGIN_NV04(push, NV50_CP(GLOBAL_ADDRESS_HIGH(15)), 2);
105 PUSH_DATA (push, 0);
106 PUSH_DATA (push, 0);
107 BEGIN_NV04(push, NV50_CP(GLOBAL_LIMIT(15)), 1);
108 PUSH_DATA (push, ~0);
109 BEGIN_NV04(push, NV50_CP(GLOBAL_MODE(15)), 1);
110 PUSH_DATA (push, NV50_COMPUTE_GLOBAL_MODE_LINEAR);
112 BEGIN_NV04(push, NV50_CP(LOCAL_WARPS_LOG_ALLOC), 1);
113 PUSH_DATA (push, 7);
114 BEGIN_NV04(push, NV50_CP(LOCAL_WARPS_NO_CLAMP), 1);
115 PUSH_DATA (push, 1);
116 BEGIN_NV04(push, NV50_CP(STACK_WARPS_LOG_ALLOC), 1);
117 PUSH_DATA (push, 7);
118 BEGIN_NV04(push, NV50_CP(STACK_WARPS_NO_CLAMP), 1);
119 PUSH_DATA (push, 1);
120 BEGIN_NV04(push, NV50_CP(USER_PARAM_COUNT), 1);
121 PUSH_DATA (push, 0);
123 BEGIN_NV04(push, NV50_CP(DMA_TEXTURE), 1);
124 PUSH_DATA (push, fifo->vram);
125 BEGIN_NV04(push, NV50_CP(TEX_LIMITS), 1);
126 PUSH_DATA (push, 0x54);
127 BEGIN_NV04(push, NV50_CP(LINKED_TSC), 1);
128 PUSH_DATA (push, 0);
130 BEGIN_NV04(push, NV50_CP(DMA_TIC), 1);
131 PUSH_DATA (push, fifo->vram);
132 BEGIN_NV04(push, NV50_CP(TIC_ADDRESS_HIGH), 3);
133 PUSH_DATAh(push, screen->txc->offset);
134 PUSH_DATA (push, screen->txc->offset);
135 PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1);
137 BEGIN_NV04(push, NV50_CP(DMA_TSC), 1);
138 PUSH_DATA (push, fifo->vram);
139 BEGIN_NV04(push, NV50_CP(TSC_ADDRESS_HIGH), 3);
140 PUSH_DATAh(push, screen->txc->offset + 65536);
141 PUSH_DATA (push, screen->txc->offset + 65536);
142 PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1);
144 BEGIN_NV04(push, NV50_CP(DMA_CODE_CB), 1);
145 PUSH_DATA (push, fifo->vram);
147 BEGIN_NV04(push, NV50_CP(DMA_LOCAL), 1);
148 PUSH_DATA (push, fifo->vram);
149 BEGIN_NV04(push, NV50_CP(LOCAL_ADDRESS_HIGH), 2);
150 PUSH_DATAh(push, screen->tls_bo->offset + 65536);
151 PUSH_DATA (push, screen->tls_bo->offset + 65536);
152 BEGIN_NV04(push, NV50_CP(LOCAL_SIZE_LOG), 1);
153 PUSH_DATA (push, util_logbase2((screen->max_tls_space / ONE_TEMP_SIZE) * 2));
198 struct nouveau_pushbuf *push = screen->base.pushbuf;
201 BEGIN_NV04(push, NV50_CP(USER_PARAM_COUNT), 1);
202 PUSH_DATA (push, (size / 4) << 8);
216 nouveau_pushbuf_bufctx(push, nv50->bufctx);
217 nouveau_pushbuf_validate(push);
219 BEGIN_NV04(push, NV50_CP(USER_PARAM(0)), size / 4);
220 nouveau_pushbuf_data(push, bo, offset, size);
247 struct nouveau_pushbuf *push = nv50->base.pushbuf;
260 BEGIN_NV04(push, NV50_CP(CP_START_ID), 1);
261 PUSH_DATA (push, nv50_compute_find_symbol(nv50, info->pc));
263 BEGIN_NV04(push, NV50_CP(SHARED_SIZE), 1);
264 PUSH_DATA (push, align(cp->cp.smem_size + cp->parm_size + 0x10, 0x40));
265 BEGIN_NV04(push, NV50_CP(CP_REG_ALLOC_TEMP), 1);
266 PUSH_DATA (push, cp->max_gpr);
269 BEGIN_NV04(push, NV50_CP(BLOCKDIM_XY), 2);
270 PUSH_DATA (push, info->block[1] << 16 | info->block[0]);
271 PUSH_DATA (push, info->block[2]);
272 BEGIN_NV04(push, NV50_CP(BLOCK_ALLOC), 1);
273 PUSH_DATA (push, 1 << 16 | block_size);
274 BEGIN_NV04(push, NV50_CP(BLOCKDIM_LATCH), 1);
275 PUSH_DATA (push, 1);
276 BEGIN_NV04(push, NV50_CP(GRIDDIM), 1);
277 PUSH_DATA (push, info->grid[1] << 16 | info->grid[0]);
278 BEGIN_NV04(push, NV50_CP(GRIDID), 1);
279 PUSH_DATA (push, 1);
282 BEGIN_NV04(push, NV50_CP(LAUNCH), 1);
283 PUSH_DATA (push, 0);
284 BEGIN_NV04(push, SUBC_CP(NV50_GRAPH_SERIALIZE), 1);
285 PUSH_DATA (push, 0);
