Lines Matching refs:info
92 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info)
96 for (n = 0, i = 0; i < info->numInputs; ++i) {
97 switch (info->in[i].sn) {
100 info->in[i].mask = 0x1;
101 info->in[i].slot[0] =
102 nvc0_shader_input_address(info->in[i].sn, 0) / 4;
108 info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4;
116 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
121 for (i = 0; i < info->numInputs; ++i) {
122 offset = nvc0_shader_input_address(info->in[i].sn, info->in[i].si);
125 info->in[i].slot[c] = (offset + c * 0x4) / 4;
132 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
134 unsigned count = info->prop.fp.numColourResults * 4;
137 for (i = 0; i < info->numOutputs; ++i)
138 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
140 info->out[i].slot[c] = info->out[i].si * 4 + c;
142 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
143 info->out[info->io.sampleMask].slot[0] = count++;
145 if (info->target >= 0xe0)
148 if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS)
149 info->out[info->io.fragDepth].slot[2] = count;
155 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
160 for (i = 0; i < info->numOutputs; ++i) {
161 offset = nvc0_shader_output_address(info->out[i].sn, info->out[i].si);
164 info->out[i].slot[c] = (offset + c * 0x4) / 4;
171 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info)
175 if (info->type == PIPE_SHADER_VERTEX)
176 ret = nvc0_vp_assign_input_slots(info);
178 ret = nvc0_sp_assign_input_slots(info);
182 if (info->type == PIPE_SHADER_FRAGMENT)
183 ret = nvc0_fp_assign_output_slots(info);
185 ret = nvc0_sp_assign_output_slots(info);
203 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
207 for (i = 0; i < info->numInputs; ++i) {
208 if (info->in[i].patch)
211 a = info->in[i].slot[c];
212 if (info->in[i].mask & (1 << c))
217 for (i = 0; i < info->numOutputs; ++i) {
218 if (info->out[i].patch)
221 if (!(info->out[i].mask & (1 << c)))
223 assert(info->out[i].slot[c] >= 0x40 / 4);
224 a = info->out[i].slot[c] - 0x40 / 4;
226 if (info->out[i].oread)
227 nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]);
231 for (i = 0; i < info->numSysVals; ++i) {
232 switch (info->sv[i].sn) {
255 vp->vp.clip_enable = (1 << info->io.clipDistances) - 1;
257 ((1 << info->io.cullDistances) - 1) << info->io.clipDistances;
258 for (i = 0; i < info->io.cullDistances; ++i)
259 vp->vp.clip_mode |= 1 << ((info->io.clipDistances + i) * 4);
261 if (info->io.genUserClip < 0)
268 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info)
273 return nvc0_vtgp_gen_header(vp, info);
277 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info)
279 if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) {
283 switch (info->prop.tp.domain) {
301 if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS) {
302 if (info->prop.tp.domain == PIPE_PRIM_LINES)
309 if (info->prop.tp.domain != PIPE_PRIM_LINES &&
310 info->prop.tp.outputPrim != PIPE_PRIM_POINTS &&
311 info->prop.tp.winding > 0)
314 switch (info->prop.tp.partitioning) {
331 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
335 tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
337 if (info->numPatchConstants)
338 opcs = 8 + info->numPatchConstants * 4;
343 tcp->hdr[2] = info->prop.tp.outputPatchSize << 24;
347 nvc0_vtgp_gen_header(tcp, info);
349 if (info->target >= NVISA_GM107_CHIPSET) {
358 nvc0_tp_get_tess_mode(tcp, info);
364 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
371 nvc0_vtgp_gen_header(tep, info);
373 nvc0_tp_get_tess_mode(tep, info);
381 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info)
385 gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24;
387 switch (info->prop.gp.outputPrim) {
405 gp->hdr[4] = CLAMP(info->prop.gp.maxVertices, 1, 1024);
407 return nvc0_vtgp_gen_header(gp, info);
426 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
434 if (info->prop.fp.usesDiscard)
436 if (info->prop.fp.numColourResults > 1)
438 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
440 if (info->prop.fp.writesDepth) {
445 for (i = 0; i < info->numInputs; ++i) {
446 m = nvc0_hdr_interp_mode(&info->in[i]);
447 if (info->in[i].sn == TGSI_SEMANTIC_COLOR) {
448 fp->fp.colors |= 1 << info->in[i].si;
449 if (info->in[i].sc)
450 fp->fp.color_interp[info->in[i].si] = m | (info->in[i].mask << 4);
453 if (!(info->in[i].mask & (1 << c)))
455 a = info->in[i].slot[c];
456 if (info->in[i].slot[0] >= (0x060 / 4) &&
457 info->in[i].slot[0] <= (0x07c / 4)) {
460 if (info->in[i].slot[0] >= (0x2c0 / 4) &&
461 info->in[i].slot[0] <= (0x2fc / 4)) {
464 if (info->in[i].slot[c] < (0x040 / 4) ||
465 info->in[i].slot[c] > (0x380 / 4))
468 if (info->in[i].slot[0] >= (0x300 / 4))
475 for (i = 0; i < info->numOutputs; ++i) {
476 if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
477 fp->hdr[18] |= 0xf << info->out[i].slot[0];
484 if (info->prop.fp.numColourResults == 0 && !info->prop.fp.writesDepth)
487 fp->fp.early_z = info->prop.fp.earlyFragTests;
488 fp->fp.sample_mask_in = info->prop.fp.usesSampleMaskIn;
489 fp->fp.reads_framebuffer = info->prop.fp.readsFramebuffer;
499 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
520 if (r >= info->numOutputs)
524 tfb->varying_index[b][p++] = info->out[r].slot[s + c];
561 struct nv50_ir_prog_info *info;
564 info = CALLOC_STRUCT(nv50_ir_prog_info);
565 if (!info)
568 info->type = prog->type;
569 info->target = chipset;
570 info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
571 info->bin.source = (void *)prog->pipe.tokens;
574 info->target = debug_get_num_option("NV50_PROG_CHIPSET", chipset);
575 info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
576 info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
578 info->optLevel = 3;
581 info->io.genUserClip = prog->vp.num_ucps;
582 info->io.auxCBSlot = 15;
583 info->io.msInfoCBSlot = 15;
584 info->io.ucpBase = NVC0_CB_AUX_UCP_INFO;
585 info->io.drawInfoBase = NVC0_CB_AUX_DRAW_INFO;
586 info->io.msInfoBase = NVC0_CB_AUX_MS_INFO;
587 info->io.bufInfoBase = NVC0_CB_AUX_BUF_INFO(0);
588 info->io.suInfoBase = NVC0_CB_AUX_SU_INFO(0);
589 if (info->target >= NVISA_GK104_CHIPSET) {
590 info->io.texBindBase = NVC0_CB_AUX_TEX_INFO(0);
591 info->io.fbtexBindBase = NVC0_CB_AUX_FB_TEX_INFO;
595 if (info->target >= NVISA_GK104_CHIPSET) {
596 info->io.auxCBSlot = 7;
597 info->io.msInfoCBSlot = 7;
598 info->io.uboInfoBase = NVC0_CB_AUX_UBO_INFO(0);
600 info->prop.cp.gridInfoBase = NVC0_CB_AUX_GRID_INFO(0);
602 info->io.sampleInfoBase = NVC0_CB_AUX_SAMPLE_INFO;
605 info->assignSlots = nvc0_program_assign_varying_slots;
607 ret = nv50_ir_generate_code(info);
613 FREE(info->bin.syms);
615 prog->code = info->bin.code;
616 prog->code_size = info->bin.codeSize;
617 prog->relocs = info->bin.relocData;
618 prog->fixups = info->bin.fixupData;
619 prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
620 prog->num_barriers = info->numBarriers;
622 prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
623 prog->vp.need_draw_parameters = info->prop.vp.usesDrawParameters;
625 if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS)
626 info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */
627 prog->vp.edgeflag = info->io.edgeFlagIn;
631 ret = nvc0_vp_gen_header(prog, info);
634 ret = nvc0_tcp_gen_header(prog, info);
637 ret = nvc0_tep_gen_header(prog, info);
640 ret = nvc0_gp_gen_header(prog, info);
643 ret = nvc0_fp_gen_header(prog, info);
646 prog->cp.syms = info->bin.syms;
647 prog->cp.num_syms = info->bin.numSyms;
657 if (info->bin.tlsSpace) {
658 assert(info->bin.tlsSpace < (1 << 24));
660 prog->hdr[1] |= align(info->bin.tlsSpace, 0x10); /* l[] size */
667 if ((info->maxCFDepth * 2) > 16) {
668 prog->hdr[2] |= (((info->maxCFDepth * 2) + 47) / 48) * 0x200;
672 if (info->io.globalAccess)
674 if (info->io.globalAccess & 0x2)
676 if (info->io.fp64)
680 prog->tfb = nvc0_program_create_tfb_state(info,
685 prog->type, info->bin.tlsSpace, prog->num_gprs,
686 info->bin.instructions, info->bin.codeSize);
689 if (debug_get_option("NV50_PROG_CHIPSET", NULL) && info->dbgFlags)
694 FREE(info);
