Lines Matching refs:enc
47 static void rate_control(struct rvce_encoder *enc)
50 RVCE_CS(enc->pic.rate_ctrl.rate_ctrl_method); // encRateControlMethod
51 RVCE_CS(enc->pic.rate_ctrl.target_bitrate); // encRateControlTargetBitRate
52 RVCE_CS(enc->pic.rate_ctrl.peak_bitrate); // encRateControlPeakBitRate
53 RVCE_CS(enc->pic.rate_ctrl.frame_rate_num); // encRateControlFrameRateNum
55 RVCE_CS(enc->pic.quant_i_frames); // encQP_I
56 RVCE_CS(enc->pic.quant_p_frames); // encQP_P
57 RVCE_CS(enc->pic.quant_b_frames); // encQP_B
58 RVCE_CS(enc->pic.rate_ctrl.vbv_buffer_size); // encVBVBufferSize
59 RVCE_CS(enc->pic.rate_ctrl.frame_rate_den); // encRateControlFrameRateDen
63 RVCE_CS(enc->pic.rate_ctrl.target_bits_picture); // encTargetBitsPerPicture
64 RVCE_CS(enc->pic.rate_ctrl.peak_bits_picture_integer); // encPeakBitsPerPictureInteger
65 RVCE_CS(enc->pic.rate_ctrl.peak_bits_picture_fraction); // encPeakBitsPerPictureFractional
79 static void encode(struct rvce_encoder *enc)
82 unsigned dep, bs_idx = enc->bs_idx++;
85 if (enc->dual_inst) {
88 else if (enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR)
95 enc->task_info(enc, 0x00000003, dep, 0, bs_idx);
98 RVCE_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0); // encodeContextAddressHi/Lo
101 bs_offset = -(signed)(bs_idx * enc->bs_size);
104 RVCE_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, bs_offset); // videoBitstreamRingAddressHi/Lo
105 RVCE_CS(enc->bs_size); // videoBitstreamRingSize
108 if (enc->dual_pipe) {
109 unsigned aux_offset = enc->cpb.res->buf->size -
122 RVCE_CS(enc->pic.frame_num ? 0x0 : 0x11); // insertHeaders
124 RVCE_CS(enc->bs_size); // allowedMaxBitstreamSize
129 RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
130 enc->luma->level[0].offset); // inputPictureLumaAddressHi/Lo
131 RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
132 enc->chroma->level[0].offset); // inputPictureChromaAddressHi/Lo
133 RVCE_CS(align(enc->luma->level[0].nblk_y, 16)); // encInputFrameYPitch
134 RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
135 RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
136 if (enc->dual_pipe)
141 RVCE_CS(enc->pic.picture_type); // encPicType
142 RVCE_CS(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR); // encIdrFlag
145 RVCE_CS(!enc->pic.not_referenced); // encReferenceFlag
151 i = enc->pic.frame_num - enc->pic.ref_idx_l0;
152 if (i > 1 && enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P) {
174 if(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P ||
175 enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B) {
176 struct rvce_cpb_slot *l0 = l0_slot(enc);
177 rvce_frame_offset(enc, l0, &luma_offset, &chroma_offset);
201 if(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B) {
202 struct rvce_cpb_slot *l1 = l1_slot(enc);
203 rvce_frame_offset(enc, l1, &luma_offset, &chroma_offset);
217 rvce_frame_offset(enc, current_slot(enc), &luma_offset, &chroma_offset);
226 RVCE_CS(enc->pic.frame_num); // frameNumber
227 RVCE_CS(enc->pic.pic_order_cnt); // pictureOrderCount
236 void radeon_vce_50_get_param(struct rvce_encoder *enc, struct pipe_h264_enc_picture_desc *pic)
240 void radeon_vce_50_init(struct rvce_encoder *enc)
242 radeon_vce_40_2_2_init(enc);
245 enc->rate_control = rate_control;
246 enc->encode = encode;
