Lines Matching refs:sctx
96 struct si_context *sctx = (struct si_context *)ctx;
131 if (si_shader_create(sscreen, sctx->tm, &program->shader,
132 &sctx->b.debug)) {
172 si_shader_dump(sctx->screen, &program->shader, &sctx->b.debug,
174 if (si_shader_binary_upload(sctx->screen, &program->shader) < 0) {
186 struct si_context *sctx = (struct si_context*)ctx;
187 sctx->cs_shader_state.program = (struct si_compute*)state;
196 struct si_context *sctx = (struct si_context*)ctx;
197 struct si_compute *program = sctx->cs_shader_state.program;
220 static void si_initialize_compute(struct si_context *sctx)
222 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
235 if (sctx->b.chip_class >= CIK) {
250 if (sctx->b.chip_class <= SI) {
259 bc_va = sctx->border_color_buffer->gpu_address;
261 if (sctx->b.chip_class >= CIK) {
266 if (sctx->screen->b.info.drm_major == 3 ||
267 (sctx->screen->b.info.drm_major == 2 &&
268 sctx->screen->b.info.drm_minor >= 48)) {
274 sctx->cs_shader_state.emitted_program = NULL;
275 sctx->cs_shader_state.initialized = true;
278 static bool si_setup_compute_scratch_buffer(struct si_context *sctx,
284 scratch_needed = config->scratch_bytes_per_wave * sctx->scratch_waves;
285 if (sctx->compute_scratch_buffer)
286 scratch_bo_size = sctx->compute_scratch_buffer->b.b.width0;
289 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
291 sctx->compute_scratch_buffer = (struct r600_resource*)
292 pipe_buffer_create(&sctx->screen->b.b, 0,
295 if (!sctx->compute_scratch_buffer)
299 if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
300 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
302 si_shader_apply_scratch_relocs(sctx, shader, config, scratch_va);
304 if (si_shader_binary_upload(sctx->screen, shader))
308 sctx->compute_scratch_buffer);
314 static bool si_switch_compute_shader(struct si_context *sctx,
320 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
325 if (sctx->cs_shader_state.emitted_program == program &&
326 sctx->cs_shader_state.offset == offset)
347 if (sctx->b.chip_class <= SI) {
360 if (!si_setup_compute_scratch_buffer(sctx, shader, config))
364 COMPUTE_DBG(sctx->screen, "Waves: %u; Scratch per wave: %u bytes; "
365 "Total Scratch: %u bytes\n", sctx->scratch_waves,
368 sctx->scratch_waves);
370 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
382 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo,
393 COMPUTE_DBG(sctx->screen, "COMPUTE_PGM_RSRC1: 0x%08x "
397 S_00B860_WAVES(sctx->scratch_waves)
400 sctx->cs_shader_state.emitted_program = program;
401 sctx->cs_shader_state.offset = offset;
402 sctx->cs_shader_state.uses_scratch =
408 static void setup_scratch_rsrc_user_sgprs(struct si_context *sctx,
412 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
413 uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
432 if (sctx->screen->b.chip_class < VI) {
447 static void si_setup_user_sgprs_co_v2(struct si_context *sctx,
452 struct si_compute *program = sctx->cs_shader_state.program;
453 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
465 setup_scratch_rsrc_user_sgprs(sctx, code_object,
494 u_upload_data(sctx->b.uploader, 0, sizeof(dispatch), 256,
502 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, dispatch_buf,
538 static void si_upload_compute_input(struct si_context *sctx,
542 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
543 struct si_compute *program = sctx->cs_shader_state.program;
556 u_upload_alloc(sctx->b.uploader, 0, kernel_args_size, 256,
576 COMPUTE_DBG(sctx->screen, "input %u : %u\n", i,
581 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, input_buffer,
585 si_setup_user_sgprs_co_v2(sctx, code_object, info, kernel_args_va);
596 static void si_setup_tgsi_grid(struct si_context *sctx,
599 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
608 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
622 struct si_compute *program = sctx->cs_shader_state.program;
636 static void si_emit_dispatch_packets(struct si_context *sctx,
639 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
640 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
655 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
683 struct si_context *sctx = (struct si_context*)ctx;
684 struct si_compute *program = sctx->cs_shader_state.program;
695 (sctx->b.chip_class == SI ||
696 sctx->b.family == CHIP_BONAIRE ||
697 sctx->b.family == CHIP_KABINI) &&
701 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
704 si_decompress_compute_textures(sctx);
715 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
720 si_need_cs_space(sctx);
722 if (!sctx->cs_shader_state.initialized)
723 si_initialize_compute(sctx);
725 if (sctx->b.flags)
726 si_emit_cache_flush(sctx);
728 if (!si_switch_compute_shader(sctx, program, &program->shader,
732 si_upload_compute_shader_descriptors(sctx);
733 si_emit_compute_shader_userdata(sctx);
735 if (si_is_atom_dirty(sctx, sctx->atoms.s.render_cond)) {
736 sctx->atoms.s.render_cond->emit(&sctx->b,
737 sctx->atoms.s.render_cond);
738 si_set_atom_dirty(sctx, sctx->atoms.s.render_cond, false);
742 si_upload_compute_input(sctx, code_object, info);
751 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, buffer,
757 si_setup_tgsi_grid(sctx, info);
759 si_ce_pre_draw_synchronization(sctx);
761 si_emit_dispatch_packets(sctx, info);
763 si_ce_post_draw_synchronization(sctx);
765 sctx->compute_is_busy = true;
766 sctx->b.num_compute_calls++;
767 if (sctx->cs_shader_state.uses_scratch)
768 sctx->b.num_spill_compute_calls++;
771 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
777 struct si_context *sctx = (struct si_context*)ctx;
783 if (program == sctx->cs_shader_state.program)
784 sctx->cs_shader_state.program = NULL;
786 if (program == sctx->cs_shader_state.emitted_program)
787 sctx->cs_shader_state.emitted_program = NULL;
797 void si_init_compute_functions(struct si_context *sctx)
799 sctx->b.b.create_compute_state = si_create_compute_state;
800 sctx->b.b.delete_compute_state = si_delete_compute_state;
801 sctx->b.b.bind_compute_state = si_bind_compute_state;
803 sctx->b.b.set_compute_resources = si_set_compute_resources;
804 sctx->b.b.set_global_binding = si_set_global_binding;
805 sctx->b.b.launch_grid = si_launch_grid;
