Lines Matching refs:sctx
93 static void si_emit_derived_tess_state(struct si_context *sctx,
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_shader_ctx_state *ls = &sctx->vs_shader;
99 /* The TES pointer will only be used for sctx->last_tcs.
102 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
103 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
113 if (sctx->last_ls == ls->current &&
114 sctx->last_tcs == tcs &&
115 sctx->last_tes_sh_base == tes_sh_base &&
116 sctx->last_num_tcs_input_cp == num_tcs_input_cp) {
117 *num_patches = sctx->last_num_patches;
121 sctx->last_ls = ls->current;
122 sctx->last_tcs = tcs;
123 sctx->last_tes_sh_base = tes_sh_base;
124 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
130 if (sctx->tcs_shader.cso) {
158 hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
164 (sctx->screen->tess_offchip_block_dw_size * 4) /
173 if (sctx->b.chip_class == SI) {
178 sctx->last_num_patches = *num_patches;
186 if (sctx->b.chip_class >= CIK) {
193 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
198 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
244 if (sctx->b.chip_class >= CIK)
264 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
268 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
280 if (sctx->gs_shader.cso)
283 if (sctx->tes_shader.cso) {
288 if ((sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
289 sctx->tes_shader.cso->info.uses_primid)
293 if ((sctx->b.family == CHIP_TAHITI ||
294 sctx->b.family == CHIP_PITCAIRN ||
295 sctx->b.family == CHIP_BONAIRE) &&
296 sctx->gs_shader.cso)
300 if (sctx->screen->has_distributed_tess) {
301 if (sctx->gs_shader.cso) {
305 if (sctx->b.family == CHIP_TONGA ||
306 sctx->b.family == CHIP_FIJI ||
307 sctx->b.family == CHIP_POLARIS10 ||
308 sctx->b.family == CHIP_POLARIS11)
318 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
323 if (sctx->b.chip_class >= CIK) {
331 if (sctx->b.screen->info.max_se < 4 ||
337 (sctx->b.family < CHIP_POLARIS10 ||
347 if (sctx->b.family == CHIP_HAWAII &&
356 if (sctx->b.chip_class <= VI &&
357 sctx->b.screen->info.max_se >= 4 &&
364 if (sctx->b.screen->info.max_se > 2 && !wd_switch_on_eop)
369 (sctx->b.family == CHIP_HAWAII ||
370 (sctx->b.chip_class == VI &&
371 (sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
375 if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
383 if (sctx->b.family == CHIP_HAWAII &&
384 sctx->gs_shader.cso &&
389 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
401 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
409 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
410 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ?
414 static void si_emit_scratch_reloc(struct si_context *sctx)
416 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
418 if (!sctx->emit_scratch_reloc)
422 sctx->spi_tmpring_size);
424 if (sctx->scratch_buffer) {
425 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
426 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
430 sctx->emit_scratch_reloc = false;
434 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
436 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
437 unsigned rast_prim = sctx->current_rast_prim;
438 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
448 if (rast_prim == sctx->last_rast_prim &&
449 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
459 sctx->last_rast_prim = rast_prim;
460 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
463 static void si_emit_draw_registers(struct si_context *sctx,
466 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
468 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
474 if (sctx->b.family >= CHIP_POLARIS10) {
475 struct si_shader_selector *tes = sctx->tes_shader.cso;
483 if (vtx_reuse_depth != sctx->last_vtx_reuse_depth) {
486 sctx->last_vtx_reuse_depth = vtx_reuse_depth;
490 if (sctx->tes_shader.cso)
491 si_emit_derived_tess_state(sctx, info, &num_patches);
493 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
496 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
497 if (sctx->b.chip_class >= CIK)
502 sctx->last_multi_vgt_param = ia_multi_vgt_param;
504 if (prim != sctx->last_prim) {
505 if (sctx->b.chip_class >= CIK)
510 sctx->last_prim = prim;
513 if (gs_out_prim != sctx->last_gs_out_prim) {
515 sctx->last_gs_out_prim = gs_out_prim;
519 if (info->primitive_restart != sctx->last_primitive_restart_en) {
521 sctx->last_primitive_restart_en = info->primitive_restart;
525 (info->restart_index != sctx->last_restart_index ||
526 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
529 sctx->last_restart_index = info->restart_index;
533 static void si_emit_draw_packets(struct si_context *sctx,
537 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
538 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
539 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
561 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
568 if (ib->index_size != sctx->last_index_size) {
578 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
583 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
591 sctx->last_index_size = ib->index_size;
598 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
605 if (sctx->b.chip_class >= CIK)
606 sctx->last_index_size = -1;
618 if (base_vertex != sctx->last_base_vertex ||
619 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
620 info->start_instance != sctx->last_start_instance ||
621 info->drawid != sctx->last_drawid ||
622 sh_base_reg != sctx->last_sh_base_reg) {
628 sctx->last_base_vertex = base_vertex;
629 sctx->last_start_instance = info->start_instance;
630 sctx->last_drawid = info->drawid;
631 sctx->last_sh_base_reg = sh_base_reg;
638 si_invalidate_draw_sh_constants(sctx);
645 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
665 if (!sctx->screen->has_draw_indirect_multi) {
681 &sctx->b, &sctx->b.gfx, params_buf,
734 void si_emit_cache_flush(struct si_context *sctx)
736 struct r600_common_context *rctx = &sctx->b;
741 sctx->b.num_fb_cache_flushes++;
812 sctx->compute_is_busy) {
816 sctx->compute_is_busy = false;
861 sctx->b.num_L2_invalidates++;
877 sctx->b.num_L2_writebacks++;
904 static void si_get_draw_start_count(struct si_context *sctx,
916 data = pipe_buffer_map_range(&sctx->b.b,
924 pipe_buffer_unmap(&sctx->b.b, transfer);
935 data = pipe_buffer_map_range(&sctx->b.b, info->indirect,
954 pipe_buffer_unmap(&sctx->b.b, transfer);
968 void si_ce_pre_draw_synchronization(struct si_context *sctx)
970 if (sctx->ce_need_synchronization) {
971 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
972 radeon_emit(sctx->ce_ib, 1);
974 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
975 radeon_emit(sctx->b.gfx.cs, 1);
979 void si_ce_post_draw_synchronization(struct si_context *sctx)
981 if (sctx->ce_need_synchronization) {
982 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
983 radeon_emit(sctx->b.gfx.cs, 0);
985 sctx->ce_need_synchronization = false;
989 static void cik_prefetch_shader_async(struct si_context *sctx,
996 cik_prefetch_TC_L2_async(sctx, bo, 0, bo->width0);
1002 struct si_context *sctx = (struct si_context *)ctx;
1003 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1021 if (unlikely(!sctx->vs_shader.cso)) {
1025 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
1029 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
1035 dirty_fb_counter = p_atomic_read(&sctx->b.screen->dirty_fb_counter);
1036 if (unlikely(dirty_fb_counter != sctx->b.last_dirty_fb_counter)) {
1037 sctx->b.last_dirty_fb_counter = dirty_fb_counter;
1038 sctx->framebuffer.dirty_cbufs |=
1039 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1040 sctx->framebuffer.dirty_zsbuf = true;
1041 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
1045 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_descriptor_counter);
1046 if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_descriptor_counter)) {
1047 sctx->b.last_dirty_tex_descriptor_counter = dirty_tex_counter;
1048 si_update_all_texture_descriptors(sctx);
1051 si_decompress_graphics_textures(sctx);
1058 if (sctx->gs_shader.cso)
1059 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1060 else if (sctx->tes_shader.cso)
1061 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1065 if (rast_prim != sctx->current_rast_prim) {
1066 sctx->current_rast_prim = rast_prim;
1067 sctx->do_update_shaders = true;
1070 if (sctx->gs_shader.cso) {
1078 !sctx->tes_shader.cso &&
1082 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1083 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1084 sctx->do_update_shaders = true;
1088 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1091 if (!si_upload_graphics_shader_descriptors(sctx))
1096 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
1097 ib.user_buffer = sctx->index_buffer.user_buffer;
1098 ib.index_size = sctx->index_buffer.index_size;
1099 ib.offset = sctx->index_buffer.offset;
1103 if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
1108 si_get_draw_start_count(sctx, info, &start, &count);
1111 u_upload_alloc(sctx->b.uploader, start_offset, count * 2, 256,
1118 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0, 0,
1131 si_get_draw_start_count(sctx, info, &start, &count);
1134 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
1145 if (info->indexed && sctx->b.chip_class <= CIK &&
1147 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1152 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1158 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1163 if (sctx->emit_scratch_reloc && sctx->scratch_buffer)
1164 r600_context_add_resource_size(ctx, &sctx->scratch_buffer->b.b);
1168 si_need_cs_space(sctx);
1174 if (!si_upload_vertex_buffer_descriptors(sctx))
1178 if (sctx->b.flags)
1179 si_emit_cache_flush(sctx);
1182 if (sctx->b.chip_class >= CIK) {
1183 if (si_pm4_state_changed(sctx, ls))
1184 cik_prefetch_shader_async(sctx, sctx->queued.named.ls);
1185 if (si_pm4_state_changed(sctx, hs))
1186 cik_prefetch_shader_async(sctx, sctx->queued.named.hs);
1187 if (si_pm4_state_changed(sctx, es))
1188 cik_prefetch_shader_async(sctx, sctx->queued.named.es);
1189 if (si_pm4_state_changed(sctx, gs))
1190 cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
1191 if (si_pm4_state_changed(sctx, vs))
1192 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
1196 if (sctx->vertex_buffer_pointer_dirty) {
1197 cik_prefetch_TC_L2_async(sctx, &sctx->vertex_buffers.buffer->b.b,
1198 sctx->vertex_buffers.buffer_offset,
1199 sctx->vertex_elements->count * 16);
1201 if (si_pm4_state_changed(sctx, ps))
1202 cik_prefetch_shader_async(sctx, sctx->queued.named.ps);
1206 mask = sctx->dirty_atoms;
1208 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
1210 atom->emit(&sctx->b, atom);
1212 sctx->dirty_atoms = 0;
1214 si_pm4_emit_dirty(sctx);
1215 si_emit_scratch_reloc(sctx);
1216 si_emit_rasterizer_prim_state(sctx);
1217 si_emit_draw_registers(sctx, info);
1219 si_ce_pre_draw_synchronization(sctx);
1221 si_emit_draw_packets(sctx, info, &ib);
1223 si_ce_post_draw_synchronization(sctx);
1225 if (sctx->trace_buf)
1226 si_trace_emit(sctx);
1230 if ((sctx->b.family == CHIP_HAWAII ||
1231 sctx->b.family == CHIP_TONGA ||
1232 sctx->b.family == CHIP_FIJI) &&
1233 r600_get_strmout_en(&sctx->b)) {
1234 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1238 if (sctx->framebuffer.state.zsbuf) {
1239 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1248 if (sctx->framebuffer.compressed_cb_mask) {
1251 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1255 surf = sctx->framebuffer.state.cbufs[i];
1266 sctx->b.num_draw_calls++;
1267 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1268 sctx->b.num_spill_draw_calls++;
1271 void si_trace_emit(struct si_context *sctx)
1273 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1275 sctx->trace_id++;
1276 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
1282 radeon_emit(cs, sctx->trace_buf->gpu_address);
1283 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
1284 radeon_emit(cs, sctx->trace_id);
1286 radeon_emit(cs, AC_ENCODE_TRACE_POINT(sctx->trace_id));
