Lines Matching refs:tc
42 sp_alloc_tile(struct softpipe_tile_cache *tc);
93 struct softpipe_tile_cache *tc;
107 tc = CALLOC_STRUCT( softpipe_tile_cache );
108 if (tc) {
109 tc->pipe = pipe;
110 for (pos = 0; pos < ARRAY_SIZE(tc->tile_addrs); pos++) {
111 tc->tile_addrs[pos].bits.invalid = 1;
113 tc->last_tile_addr.bits.invalid = 1;
118 tc->tile = MALLOC_STRUCT( softpipe_cached_tile );
119 if (!tc->tile)
121 FREE(tc);
132 memset(tc->clear_flags, 255, sizeof(tc->clear_flags));
135 return tc;
140 sp_destroy_tile_cache(struct softpipe_tile_cache *tc)
142 if (tc) {
145 for (pos = 0; pos < ARRAY_SIZE(tc->entries); pos++) {
146 /*assert(tc->entries[pos].x < 0);*/
147 FREE( tc->entries[pos] );
149 FREE( tc->tile );
151 if (tc->num_maps) {
153 for (i = 0; i < tc->num_maps; i++)
154 if (tc->transfer[i]) {
155 tc->pipe->transfer_unmap(tc->pipe, tc->transfer[i]);
157 FREE(tc->transfer);
158 FREE(tc->transfer_map);
159 FREE(tc->clear_flags);
162 FREE( tc );
171 sp_tile_cache_set_surface(struct softpipe_tile_cache *tc,
174 struct pipe_context *pipe = tc->pipe;
177 if (tc->num_maps) {
178 if (ps == tc->surface)
181 for (i = 0; i < tc->num_maps; i++) {
182 pipe->transfer_unmap(pipe, tc->transfer[i]);
183 tc->transfer[i] = NULL;
184 tc->transfer_map[i] = NULL;
186 FREE(tc->transfer);
187 FREE(tc->transfer_map);
188 tc->num_maps = 0;
190 FREE(tc->clear_flags);
191 tc->clear_flags_size = 0;
194 tc->surface = ps;
197 tc->num_maps = ps->u.tex.last_layer - ps->u.tex.first_layer + 1;
198 tc->transfer = CALLOC(tc->num_maps, sizeof(struct pipe_transfer *));
199 tc->transfer_map = CALLOC(tc->num_maps, sizeof(void *));
201 tc->clear_flags_size = (MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) * tc->num_maps / 32 * sizeof(uint);
202 tc->clear_flags = CALLOC(1, tc->clear_flags_size);
205 for (i = 0; i < tc->num_maps; i++) {
206 tc->transfer_map[i] = pipe_transfer_map(pipe, ps->texture,
211 &tc->transfer[i]);
219 tc->depth_stencil = util_format_is_depth_or_stencil(ps->format);
228 sp_tile_cache_get_surface(struct softpipe_tile_cache *tc)
230 return tc->surface;
343 sp_tile_cache_flush_clear(struct softpipe_tile_cache *tc, int layer)
345 struct pipe_transfer *pt = tc->transfer[layer];
346 const uint w = tc->transfer[layer]->box.width;
347 const uint h = tc->transfer[layer]->box.height;
354 if (tc->depth_stencil) {
355 clear_tile(tc->tile, pt->resource->format, tc->clear_val);
357 clear_tile_rgba(tc->tile, pt->resource->format, &tc->clear_color);
365 if (is_clear_flag_set(tc->clear_flags, addr, tc->clear_flags_size)) {
367 if (tc->depth_stencil) {
368 pipe_put_tile_raw(pt, tc->transfer_map[layer],
370 tc->tile->data.any, 0/*STRIDE*/);
373 if (util_format_is_pure_uint(tc->surface->format)) {
374 pipe_put_tile_ui_format(pt, tc->transfer_map[layer],
377 (unsigned *) tc->tile->data.colorui128);
378 } else if (util_format_is_pure_sint(tc->surface->format)) {
379 pipe_put_tile_i_format(pt, tc->transfer_map[layer],
382 (int *) tc->tile->data.colori128);
384 pipe_put_tile_rgba(pt, tc->transfer_map[layer],
386 (float *) tc->tile->data.color);
401 sp_flush_tile(struct softpipe_tile_cache* tc, unsigned pos)
403 int layer = tc->tile_addrs[pos].bits.layer;
404 if (!tc->tile_addrs[pos].bits.invalid) {
405 if (tc->depth_stencil) {
406 pipe_put_tile_raw(tc->transfer[layer], tc->transfer_map[layer],
407 tc->tile_addrs[pos].bits.x * TILE_SIZE,
408 tc->tile_addrs[pos].bits.y * TILE_SIZE,
410 tc->entries[pos]->data.depth32, 0/*STRIDE*/);
413 if (util_format_is_pure_uint(tc->surface->format)) {
414 pipe_put_tile_ui_format(tc->transfer[layer], tc->transfer_map[layer],
415 tc->tile_addrs[pos].bits.x * TILE_SIZE,
416 tc->tile_addrs[pos].bits.y * TILE_SIZE,
418 tc->surface->format,
419 (unsigned *) tc->entries[pos]->data.colorui128);
420 } else if (util_format_is_pure_sint(tc->surface->format)) {
421 pipe_put_tile_i_format(tc->transfer[layer], tc->transfer_map[layer],
422 tc->tile_addrs[pos].bits.x * TILE_SIZE,
423 tc->tile_addrs[pos].bits.y * TILE_SIZE,
425 tc->surface->format,
426 (int *) tc->entries[pos]->data.colori128);
428 pipe_put_tile_rgba_format(tc->transfer[layer], tc->transfer_map[layer],
429 tc->tile_addrs[pos].bits.x * TILE_SIZE,
430 tc->tile_addrs[pos].bits.y * TILE_SIZE,
432 tc->surface->format,
433 (float *) tc->entries[pos]->data.color);
436 tc->tile_addrs[pos].bits.invalid = 1; /* mark as empty */
445 sp_flush_tile_cache(struct softpipe_tile_cache *tc)
449 if (tc->num_maps) {
451 for (pos = 0; pos < ARRAY_SIZE(tc->entries); pos++) {
452 struct softpipe_cached_tile *tile = tc->entries[pos];
455 assert(tc->tile_addrs[pos].bits.invalid);
458 sp_flush_tile(tc, pos);
462 if (!tc->tile)
463 tc->tile = sp_alloc_tile(tc);
465 for (i = 0; i < tc->num_maps; i++)
466 sp_tile_cache_flush_clear(tc, i);
468 memset(tc->clear_flags, 0, tc->clear_flags_size);
470 tc->last_tile_addr.bits.invalid = 1;
479 sp_alloc_tile(struct softpipe_tile_cache *tc)
485 if (!tc->tile)
488 for (pos = 0; pos < ARRAY_SIZE(tc->entries); ++pos) {
489 if (!tc->entries[pos])
492 sp_flush_tile(tc, pos);
493 tc->tile = tc->entries[pos];
494 tc->entries[pos] = NULL;
499 if (!tc->tile)
503 tile = tc->tile;
504 tc->tile = NULL;
506 tc->last_tile_addr.bits.invalid = 1;
516 sp_find_cached_tile(struct softpipe_tile_cache *tc,
523 struct softpipe_cached_tile *tile = tc->entries[pos];
526 tc);
527 tc->entries[pos] = tile;
530 if (addr.value != tc->tile_addrs[pos].value) {
532 layer = tc->tile_addrs[pos].bits.layer;
533 if (tc->tile_addrs[pos].bits.invalid == 0) {
535 if (tc->depth_stencil) {
536 pipe_put_tile_raw(tc->transfer[layer], tc->transfer_map[layer],
537 tc->tile_addrs[pos].bits.x * TILE_SIZE,
538 tc->tile_addrs[pos].bits.y * TILE_SIZE,
543 if (util_format_is_pure_uint(tc->surface->format)) {
544 pipe_put_tile_ui_format(tc->transfer[layer], tc->transfer_map[layer],
545 tc->tile_addrs[pos].bits.x * TILE_SIZE,
546 tc->tile_addrs[pos].bits.y * TILE_SIZE,
548 tc->surface->format,
550 } else if (util_format_is_pure_sint(tc->surface->format)) {
551 pipe_put_tile_i_format(tc->transfer[layer], tc->transfer_map[layer],
552 tc->tile_addrs[pos].bits.x * TILE_SIZE,
553 tc->tile_addrs[pos].bits.y * TILE_SIZE,
555 tc->surface->format,
558 pipe_put_tile_rgba_format(tc->transfer[layer], tc->transfer_map[layer],
559 tc->tile_addrs[pos].bits.x * TILE_SIZE,
560 tc->tile_addrs[pos].bits.y * TILE_SIZE,
562 tc->surface->format,
568 tc->tile_addrs[pos] = addr;
570 layer = tc->tile_addrs[pos].bits.layer;
571 pt = tc->transfer[layer];
574 if (is_clear_flag_set(tc->clear_flags, addr, tc->clear_flags_size)) {
576 if (tc->depth_stencil) {
577 clear_tile(tile, pt->resource->format, tc->clear_val);
580 clear_tile_rgba(tile, pt->resource->format, &tc->clear_color);
582 clear_clear_flag(tc->clear_flags, addr, tc->clear_flags_size);
586 if (tc->depth_stencil) {
587 pipe_get_tile_raw(tc->transfer[layer], tc->transfer_map[layer],
588 tc->tile_addrs[pos].bits.x * TILE_SIZE,
589 tc->tile_addrs[pos].bits.y * TILE_SIZE,
594 if (util_format_is_pure_uint(tc->surface->format)) {
595 pipe_get_tile_ui_format(tc->transfer[layer], tc->transfer_map[layer],
596 tc->tile_addrs[pos].bits.x * TILE_SIZE,
597 tc->tile_addrs[pos].bits.y * TILE_SIZE,
599 tc->surface->format,
601 } else if (util_format_is_pure_sint(tc->surface->format)) {
602 pipe_get_tile_i_format(tc->transfer[layer], tc->transfer_map[layer],
603 tc->tile_addrs[pos].bits.x * TILE_SIZE,
604 tc->tile_addrs[pos].bits.y * TILE_SIZE,
606 tc->surface->format,
609 pipe_get_tile_rgba_format(tc->transfer[layer], tc->transfer_map[layer],
610 tc->tile_addrs[pos].bits.x * TILE_SIZE,
611 tc->tile_addrs[pos].bits.y * TILE_SIZE,
613 tc->surface->format,
620 tc->last_tile = tile;
621 tc->last_tile_addr = addr;
635 sp_tile_cache_clear(struct softpipe_tile_cache *tc,
641 tc->clear_color = *color;
643 tc->clear_val = clearValue;
646 memset(tc->clear_flags, 255, tc->clear_flags_size);
648 for (pos = 0; pos < ARRAY_SIZE(tc->tile_addrs); pos++) {
649 tc->tile_addrs[pos].bits.invalid = 1;
651 tc->last_tile_addr.bits.invalid = 1;
