Lines Matching refs:emit
78 * generate extra code to emit clip distances.
226 emit_post_helpers(struct svga_shader_emitter_v10 *emit);
229 emit_vertex(struct svga_shader_emitter_v10 *emit,
235 expand(struct svga_shader_emitter_v10 *emit)
238 unsigned newsize = emit->size * 2;
240 if (emit->buf != err_buf)
241 new_buf = REALLOC(emit->buf, emit->size, newsize);
246 emit->ptr = err_buf;
247 emit->buf = err_buf;
248 emit->size = sizeof(err_buf);
252 emit->size = newsize;
253 emit->ptr = new_buf + (emit->ptr - emit->buf);
254 emit->buf = new_buf;
264 struct svga_shader_emitter_v10 *emit = CALLOC(1, sizeof(*emit));
266 if (!emit)
270 emit->size = 512;
271 if (!expand(emit)) {
272 FREE(emit);
275 return emit;
282 free_emitter(struct svga_shader_emitter_v10 *emit)
284 assert(emit);
285 FREE(emit->buf); /* will be NULL if translation succeeded */
286 FREE(emit);
290 reserve(struct svga_shader_emitter_v10 *emit,
293 while (emit->ptr - emit->buf + nr_dwords * sizeof(uint32) >= emit->size) {
294 if (!expand(emit))
302 emit_dword(struct svga_shader_emitter_v10 *emit, uint32 dword)
304 if (!reserve(emit, 1))
307 *(uint32 *)emit->ptr = dword;
308 emit->ptr += sizeof dword;
313 emit_dwords(struct svga_shader_emitter_v10 *emit,
317 if (!reserve(emit, nr))
320 memcpy(emit->ptr, dwords, nr * sizeof *dwords);
321 emit->ptr += nr * sizeof *dwords;
327 emit_get_num_tokens(const struct svga_shader_emitter_v10 *emit)
329 return (emit->ptr - emit->buf) / sizeof(unsigned);
342 check_register_index(struct svga_shader_emitter_v10 *emit,
345 bool overflow_before = emit->register_overflow;
352 emit->register_overflow = TRUE;
358 emit->register_overflow = TRUE;
369 if ((emit->unit == PIPE_SHADER_VERTEX &&
371 (emit->unit == PIPE_SHADER_GEOMETRY &&
373 (emit->unit == PIPE_SHADER_FRAGMENT &&
375 emit->register_overflow = TRUE;
382 if ((emit->unit == PIPE_SHADER_VERTEX &&
384 (emit->unit == PIPE_SHADER_GEOMETRY &&
386 (emit->unit == PIPE_SHADER_FRAGMENT &&
388 emit->register_overflow = TRUE;
394 emit->register_overflow = TRUE;
400 emit->register_overflow = TRUE;
405 emit->register_overflow = TRUE;
413 if (emit->register_overflow && !overflow_before) {
424 determine_clipping_mode(struct svga_shader_emitter_v10 *emit)
426 if (emit->info.num_written_clipdistance > 0) {
427 emit->clip_mode = CLIP_DISTANCE;
429 else if (emit->info.writes_clipvertex) {
430 emit->clip_mode = CLIP_VERTEX;
432 else if (emit->key.clip_plane_enable) {
433 emit->clip_mode = CLIP_LEGACY;
436 emit->clip_mode = CLIP_NONE;
459 apply_clip_plane_mask(struct svga_shader_emitter_v10 *emit,
468 writemask &= ((emit->key.clip_plane_enable >> shift) & 0xf);
688 * Emit a null dst register
691 emit_null_dst_register(struct svga_shader_emitter_v10 *emit)
699 emit_dword(emit, operand.value);
708 get_temp_array_id(const struct svga_shader_emitter_v10 *emit,
712 return emit->temp_map[index].arrayId;
725 remap_temp_index(const struct svga_shader_emitter_v10 *emit,
729 return emit->temp_map[index].index;
742 setup_operand0_indexing(struct svga_shader_emitter_v10 *emit,
811 * Emit the operand for expressing an address register for indirect indexing.
816 emit_indirect_register(struct svga_shader_emitter_v10 *emit,
824 tmp_reg_index = emit->address_reg_index[addr_reg_index];
838 emit_dword(emit, operand0.value);
839 emit_dword(emit, remap_temp_index(emit, TGSI_FILE_TEMPORARY, tmp_reg_index));
844 * Translate the dst register of a TGSI instruction and emit VGPU10 tokens.
845 * \param emit the emitter context
849 emit_dst_register(struct svga_shader_emitter_v10 *emit,
854 const unsigned sem_name = emit->info.output_semantic_name[index];
855 const unsigned sem_index = emit->info.output_semantic_index[index];
858 const unsigned tempArrayId = get_temp_array_id(emit, file, index);
863 if (emit->unit == PIPE_SHADER_VERTEX ||
864 emit->unit == PIPE_SHADER_GEOMETRY) {
865 if (index == emit->vposition.out_index &&
866 emit->vposition.tmp_index != INVALID_INDEX) {
872 index = emit->vposition.tmp_index;
875 emit->clip_dist_tmp_index != INVALID_INDEX) {
882 index = emit->clip_dist_tmp_index + sem_index;
885 emit->clip_vertex_tmp_index != INVALID_INDEX) {
887 assert(emit->clip_mode == CLIP_VERTEX);
890 index = emit->clip_vertex_tmp_index;
893 else if (emit->unit == PIPE_SHADER_FRAGMENT) {
900 emit_dword(emit, operand0.value);
903 else if (index == emit->fs.color_out_index[0] &&
904 emit->fs.color_tmp_index != INVALID_INDEX) {
910 index = emit->fs.color_tmp_index;
920 index = emit->info.output_semantic_index[index];
922 emit->num_output_writes++;
944 check_register_index(emit, operand0.operandType, index);
946 operand0 = setup_operand0_indexing(emit, operand0, file, indirect,
949 /* Emit tokens */
950 emit_dword(emit, operand0.value);
952 emit_dword(emit, tempArrayId);
955 emit_dword(emit, remap_temp_index(emit, file, index));
958 emit_indirect_register(emit, reg->Indirect.Index);
964 * Translate a src register of a TGSI instruction and emit VGPU10 tokens.
967 emit_src_register(struct svga_shader_emitter_v10 *emit,
973 const unsigned tempArrayId = get_temp_array_id(emit, file, index);
986 if (emit->unit == PIPE_SHADER_FRAGMENT &&
988 if (index == emit->fs.face_input_index) {
991 index = emit->fs.face_tmp_index;
993 else if (index == emit->fs.fragcoord_input_index) {
996 index = emit->fs.fragcoord_tmp_index;
1002 index = emit->linkage.input_map[index];
1005 else if (emit->unit == PIPE_SHADER_GEOMETRY &&
1007 is_prim_id = (index == emit->gs.prim_id_index);
1008 index = emit->linkage.input_map[index];
1010 else if (emit->unit == PIPE_SHADER_VERTEX) {
1013 if ((emit->key.vs.adjust_attrib_w_1 |
1014 emit->key.vs.adjust_attrib_itof |
1015 emit->key.vs.adjust_attrib_utof |
1016 emit->key.vs.attrib_is_bgra |
1017 emit->key.vs.attrib_puint_to_snorm |
1018 emit->key.vs.attrib_puint_to_uscaled |
1019 emit->key.vs.attrib_puint_to_sscaled) & (1 << index)) {
1021 index = emit->vs.adjusted_input[index];
1025 assert(index < ARRAY_SIZE(emit->system_value_indexes));
1026 index = emit->system_value_indexes[index];
1041 operand0 = setup_operand0_indexing(emit, operand0, file, indirect,
1073 /* Emit the operand tokens */
1074 emit_dword(emit, operand0.value);
1076 emit_dword(emit, operand1.value);
1079 /* Emit the four float/int in-line immediate values */
1081 assert(index < ARRAY_SIZE(emit->immediates));
1087 c = (unsigned *) emit->immediates[index];
1088 emit_dword(emit, c[swizzleX]);
1089 emit_dword(emit, c[swizzleY]);
1090 emit_dword(emit, c[swizzleZ]);
1091 emit_dword(emit, c[swizzleW]);
1094 /* Emit the register index(es) */
1097 emit_dword(emit, reg->Dimension.Index);
1101 emit_dword(emit, tempArrayId);
1104 emit_dword(emit, remap_temp_index(emit, file, index));
1107 emit_indirect_register(emit, reg->Indirect.Index);
1114 * Emit a resource operand (for use with a SAMPLE instruction).
1117 emit_resource_register(struct svga_shader_emitter_v10 *emit,
1122 check_register_index(emit, VGPU10_OPERAND_TYPE_RESOURCE, resource_number);
1136 emit_dword(emit, operand0.value);
1137 emit_dword(emit, resource_number);
1142 * Emit a sampler operand (for use with a SAMPLE instruction).
1145 emit_sampler_register(struct svga_shader_emitter_v10 *emit,
1150 check_register_index(emit, VGPU10_OPERAND_TYPE_SAMPLER, sampler_number);
1158 emit_dword(emit, operand0.value);
1159 emit_dword(emit, sampler_number);
1164 * Emit an operand which reads the IS_FRONT_FACING register.
1167 emit_face_register(struct svga_shader_emitter_v10 *emit)
1170 unsigned index = emit->linkage.input_map[emit->fs.face_input_index];
1185 emit_dword(emit, operand0.value);
1186 emit_dword(emit, index);
1191 * Emit the token for a VGPU10 opcode.
1195 emit_opcode(struct svga_shader_emitter_v10 *emit,
1205 emit_dword(emit, token0.value);
1210 * Emit the token for a VGPU10 resinfo instruction.
1216 emit_opcode_resinfo(struct svga_shader_emitter_v10 *emit,
1226 emit_dword(emit, token0.value);
1231 * Emit opcode tokens for a texture sample instruction. Texture instructions
1236 emit_sample_opcode(struct svga_shader_emitter_v10 *emit,
1264 emit_dword(emit, token0.value);
1266 emit_dword(emit, token1.value);
1272 * Emit a DISCARD opcode token.
1277 emit_discard_opcode(struct svga_shader_emitter_v10 *emit, boolean nonzero)
1286 emit_dword(emit, opcode0.value);
1294 begin_emit_instruction(struct svga_shader_emitter_v10 *emit)
1296 assert(emit->inst_start_token == 0);
1301 emit->inst_start_token = emit_get_num_tokens(emit);
1306 * We need to call this after we emit the last token of a VGPU10 instruction.
1310 end_emit_instruction(struct svga_shader_emitter_v10 *emit)
1312 VGPU10OpcodeToken0 *tokens = (VGPU10OpcodeToken0 *) emit->buf;
1315 assert(emit->inst_start_token > 0);
1317 if (emit->discard_instruction) {
1318 /* Back up the emit->ptr to where this instruction started so
1321 emit->ptr = (char *) (tokens + emit->inst_start_token);
1327 inst_length = emit_get_num_tokens(emit) - emit->inst_start_token;
1331 tokens[emit->inst_start_token].instructionLength = inst_length;
1334 emit->inst_start_token = 0; /* reset to zero for error checking */
1335 emit->discard_instruction = FALSE;
1343 get_temp_index(struct svga_shader_emitter_v10 *emit)
1345 assert(emit->internal_temp_count < MAX_INTERNAL_TEMPS);
1346 return emit->num_shader_temps + emit->internal_temp_count++;
1354 free_temp_indexes(struct svga_shader_emitter_v10 *emit)
1356 emit->internal_temp_count = 0;
1568 find_immediate(struct svga_shader_emitter_v10 *emit,
1571 const unsigned endIndex = emit->num_immediates;
1574 assert(emit->immediates_emitted);
1578 if (x.Int == emit->immediates[i][0].Int ||
1579 x.Int == emit->immediates[i][1].Int ||
1580 x.Int == emit->immediates[i][2].Int ||
1581 x.Int == emit->immediates[i][3].Int) {
1599 make_immediate_reg_4(struct svga_shader_emitter_v10 *emit,
1605 for (i = 0; i < emit->num_common_immediates; i++) {
1607 int immpos = find_immediate(emit, imm[0], i);
1613 x = find_imm_in_vec4(emit->immediates[immpos], imm[0]);
1614 y = find_imm_in_vec4(emit->immediates[immpos], imm[1]);
1615 z = find_imm_in_vec4(emit->immediates[immpos], imm[2]);
1616 w = find_imm_in_vec4(emit->immediates[immpos], imm[3]);
1647 make_immediate_reg(struct svga_shader_emitter_v10 *emit,
1651 int immpos = find_immediate(emit, value, 0);
1661 reg.Register.SwizzleW = find_imm_in_vec4(emit->immediates[immpos], value);
1672 make_immediate_reg_float4(struct svga_shader_emitter_v10 *emit,
1680 return make_immediate_reg_4(emit, imm);
1690 make_immediate_reg_float(struct svga_shader_emitter_v10 *emit, float value)
1694 return make_immediate_reg(emit, imm);
1702 make_immediate_reg_int4(struct svga_shader_emitter_v10 *emit,
1710 return make_immediate_reg_4(emit, imm);
1720 make_immediate_reg_int(struct svga_shader_emitter_v10 *emit, int value)
1724 return make_immediate_reg(emit, imm);
1733 alloc_immediate_4(struct svga_shader_emitter_v10 *emit,
1736 unsigned n = emit->num_immediates++;
1737 assert(!emit->immediates_emitted);
1738 assert(n < ARRAY_SIZE(emit->immediates));
1739 emit->immediates[n][0] = imm[0];
1740 emit->immediates[n][1] = imm[1];
1741 emit->immediates[n][2] = imm[2];
1742 emit->immediates[n][3] = imm[3];
1752 alloc_immediate_float4(struct svga_shader_emitter_v10 *emit,
1760 return alloc_immediate_4(emit, imm);
1769 alloc_immediate_int4(struct svga_shader_emitter_v10 *emit,
1777 return alloc_immediate_4(emit, imm);
1785 alloc_system_value_index(struct svga_shader_emitter_v10 *emit, unsigned index)
1787 const unsigned n = emit->info.file_max[TGSI_FILE_INPUT] + 1 + index;
1788 assert(index < ARRAY_SIZE(emit->system_value_indexes));
1789 emit->system_value_indexes[index] = n;
1798 emit_vgpu10_immediate(struct svga_shader_emitter_v10 *emit,
1801 /* We don't actually emit any code here. We just save the
1802 * immediate values and emit them later.
1804 alloc_immediate_4(emit, imm->u);
1810 * Emit a VGPU10_CUSTOMDATA_DCL_IMMEDIATE_CONSTANT_BUFFER block
1815 emit_vgpu10_immediates_block(struct svga_shader_emitter_v10 *emit)
1819 assert(!emit->immediates_emitted);
1826 emit_dword(emit, token.value);
1827 emit_dword(emit, 2 + 4 * emit->num_immediates);
1828 emit_dwords(emit, (unsigned *) emit->immediates, 4 * emit->num_immediates);
1830 emit->immediates_emitted = TRUE;
1842 translate_interpolation(const struct svga_shader_emitter_v10 *emit,
1846 interp = emit->key.fs.flatshade ?
1870 * Don't emit any instructions yet, only need to gather the primitive property information.
1875 emit_vgpu10_property(struct svga_shader_emitter_v10 *emit,
1926 emit->gs.prim_type = primType[prop->u[0].Data];
1927 assert(emit->gs.prim_type != VGPU10_PRIMITIVE_UNDEFINED);
1928 emit->gs.input_size = inputArraySize[emit->gs.prim_type];
1933 emit->gs.prim_topology = primTopology[prop->u[0].Data];
1934 assert(emit->gs.prim_topology != VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED);
1938 emit->gs.max_out_vertices = prop->u[0].Data;
1950 emit_property_instruction(struct svga_shader_emitter_v10 *emit,
1954 begin_emit_instruction(emit);
1955 emit_dword(emit, opcode0.value);
1957 emit_dword(emit, data);
1958 end_emit_instruction(emit);
1963 * Emit property instructions
1966 emit_property_instructions(struct svga_shader_emitter_v10 *emit)
1970 assert(emit->unit == PIPE_SHADER_GEOMETRY);
1972 /* emit input primitive type declaration */
1975 opcode0.primitive = emit->gs.prim_type;
1976 emit_property_instruction(emit, opcode0, 0, 0);
1978 /* emit output primitive topology declaration */
1981 opcode0.primitiveTopology = emit->gs.prim_topology;
1982 emit_property_instruction(emit, opcode0, 0, 0);
1984 /* emit max output vertices */
1987 emit_property_instruction(emit, opcode0, 1, emit->gs.max_out_vertices);
1992 * Emit a vgpu10 declaration "instruction".
1999 emit_decl_instruction(struct svga_shader_emitter_v10 *emit,
2008 begin_emit_instruction(emit);
2009 emit_dword(emit, opcode0.value);
2011 emit_dword(emit, operand0.value);
2015 emit_dword(emit, index);
2019 emit_dword(emit, size);
2022 emit_dword(emit, index);
2026 emit_dword(emit, name_token.value);
2029 end_emit_instruction(emit);
2034 * Emit the declaration for a shader input.
2049 emit_input_declaration(struct svga_shader_emitter_v10 *emit,
2083 check_register_index(emit, opcodeType, index);
2101 emit_decl_instruction(emit, opcode0, operand0, name_token, index, size);
2106 * Emit the declaration for a shader output.
2113 emit_output_declaration(struct svga_shader_emitter_v10 *emit,
2131 check_register_index(emit, type, index);
2145 emit_decl_instruction(emit, opcode0, operand0, name_token, index, 1);
2150 * Emit the declaration for the fragment depth output.
2153 emit_fragdepth_output_declaration(struct svga_shader_emitter_v10 *emit)
2159 assert(emit->unit == PIPE_SHADER_FRAGMENT);
2169 emit_decl_instruction(emit, opcode0, operand0, name_token, 0, 1);
2174 * Emit the declaration for a system value input/output.
2177 emit_system_value_declaration(struct svga_shader_emitter_v10 *emit,
2182 index = alloc_system_value_index(emit, index);
2183 emit_input_declaration(emit, VGPU10_OPCODE_DCL_INPUT_SIV,
2194 index = alloc_system_value_index(emit, index);
2195 emit_input_declaration(emit, VGPU10_OPCODE_DCL_INPUT_SIV,
2214 emit_vgpu10_declaration(struct svga_shader_emitter_v10 *emit,
2224 emit->output_usage_mask[decl->Range.First] = decl->Declaration.UsageMask;
2229 * and emit the declaration later.
2238 assert(arrayID < ARRAY_SIZE(emit->temp_arrays));
2240 /* Save this array so we can emit the declaration for it later */
2241 emit->temp_arrays[arrayID].start = decl->Range.First;
2242 emit->temp_arrays[arrayID].size =
2245 emit->num_temp_arrays = MAX2(emit->num_temp_arrays, arrayID + 1);
2246 assert(emit->num_temp_arrays <= MAX_TEMP_ARRAYS);
2247 emit->num_temp_arrays = MIN2(emit->num_temp_arrays, MAX_TEMP_ARRAYS);
2251 emit->temp_map[i].arrayId = arrayID;
2252 emit->temp_map[i].index = i - decl->Range.First;
2257 emit->num_shader_temps = MAX2(emit->num_shader_temps,
2262 /* Don't declare constants here. Just keep track and emit later. */
2272 assert(constbuf < ARRAY_SIZE(emit->num_shader_consts));
2274 num_consts = MAX2(emit->num_shader_consts[constbuf],
2284 emit->num_shader_consts[constbuf] =
2294 emit_system_value_declaration(emit, decl->Semantic.Name,
2299 /* Don't declare samplers here. Just keep track and emit later. */
2300 emit->num_samplers = MAX2(emit->num_samplers, decl->Range.Last + 1);
2312 emit->num_address_regs = MAX2(emit->num_address_regs,
2320 emit->sampler_target[unit] = decl->SamplerView.Resource;
2322 emit->sampler_return_type[unit] = decl->SamplerView.ReturnTypeX;
2335 * Emit all input declarations.
2338 emit_input_declarations(struct svga_shader_emitter_v10 *emit)
2342 if (emit->unit == PIPE_SHADER_FRAGMENT) {
2344 for (i = 0; i < emit->linkage.num_inputs; i++) {
2345 unsigned semantic_name = emit->info.input_semantic_name[i];
2346 unsigned usage_mask = emit->info.input_usage_mask[i];
2347 unsigned index = emit->linkage.input_map[i];
2360 emit->fs.fragcoord_input_index = i;
2368 emit->fs.face_input_index = i;
2380 translate_interpolation(emit,
2381 emit->info.input_interpolate[i],
2382 emit->info.input_interpolate_loc[i]);
2385 emit->uses_flat_interp = emit->uses_flat_interp ||
2391 emit_input_declaration(emit, type,
2401 else if (emit->unit == PIPE_SHADER_GEOMETRY) {
2403 for (i = 0; i < emit->info.num_inputs; i++) {
2404 unsigned semantic_name = emit->info.input_semantic_name[i];
2405 unsigned usage_mask = emit->info.input_usage_mask[i];
2406 unsigned index = emit->linkage.input_map[i];
2432 * primitive id when emit src register. We need to modify the
2433 * operand type, index dimension when emit primitive id src reg.
2435 emit->gs.prim_id_index = i;
2443 emit_input_declaration(emit, opcodeType, operandType,
2445 emit->gs.input_size,
2453 assert(emit->unit == PIPE_SHADER_VERTEX);
2455 for (i = 0; i < emit->info.file_max[TGSI_FILE_INPUT] + 1; i++) {
2456 unsigned usage_mask = emit->info.input_usage_mask[i];
2462 emit_input_declaration(emit, VGPU10_OPCODE_DCL_INPUT,
2478 * Emit all output declarations.
2481 emit_output_declarations(struct svga_shader_emitter_v10 *emit)
2485 for (i = 0; i < emit->info.num_outputs; i++) {
2486 /*const unsigned usage_mask = emit->info.output_usage_mask[i];*/
2487 const unsigned semantic_name = emit->info.output_semantic_name[i];
2488 const unsigned semantic_index = emit->info.output_semantic_index[i];
2491 if (emit->unit == PIPE_SHADER_FRAGMENT) {
2493 assert(semantic_index < ARRAY_SIZE(emit->fs.color_out_index));
2495 emit->fs.color_out_index[semantic_index] = index;
2498 emit_output_declaration(emit,
2504 if (emit->key.fs.write_color0_to_n_cbufs > 1) {
2505 /* Emit declarations for the additional color outputs
2509 for (j = 1; j < emit->key.fs.write_color0_to_n_cbufs; j++) {
2511 unsigned idx = emit->info.num_outputs + j - 1;
2512 emit->fs.color_out_index[j] = idx;
2513 emit_output_declaration(emit,
2517 emit->info.output_semantic_index[idx] = j;
2522 assert(!emit->key.fs.write_color0_to_n_cbufs);
2527 emit_fragdepth_output_declaration(emit);
2540 assert(emit->unit != PIPE_SHADER_FRAGMENT);
2544 emit->vposition.out_index = index;
2551 emit->clip_dist_out_index = index;
2552 writemask = emit->output_usage_mask[index];
2553 writemask = apply_clip_plane_mask(emit, writemask, semantic_index);
2559 assert(emit->unit == PIPE_SHADER_GEOMETRY);
2564 assert(emit->unit == PIPE_SHADER_GEOMETRY);
2571 emit->clip_vertex_out_index = index;
2579 emit_output_declaration(emit, type, index, name, writemask);
2583 if (emit->vposition.so_index != INVALID_INDEX &&
2584 emit->vposition.out_index != INVALID_INDEX) {
2586 assert(emit->unit != PIPE_SHADER_FRAGMENT);
2588 /* Emit the declaration for the non-adjusted vertex position
2591 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT,
2592 emit->vposition.so_index,
2597 if (emit->clip_dist_so_index != INVALID_INDEX &&
2598 emit->clip_dist_out_index != INVALID_INDEX) {
2600 assert(emit->unit != PIPE_SHADER_FRAGMENT);
2602 /* Emit the declaration for the clip distance shadow copy which
2606 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT,
2607 emit->clip_dist_so_index,
2609 emit->output_usage_mask[emit->clip_dist_out_index]);
2611 if (emit->info.num_written_clipdistance > 4) {
2613 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT,
2614 emit->clip_dist_so_index + 1,
2616 emit->output_usage_mask[emit->clip_dist_out_index+1]);
2625 * Emit the declaration for the temporary registers.
2628 emit_temporaries_declaration(struct svga_shader_emitter_v10 *emit)
2632 total_temps = emit->num_shader_temps;
2640 if ((emit->info.indirect_files & (1 << TGSI_FILE_TEMPORARY)) &&
2641 emit->num_temp_arrays == 0) {
2645 emit->num_temp_arrays = arrayID + 1;
2646 emit->temp_arrays[arrayID].start = 0;
2647 emit->temp_arrays[arrayID].size = total_temps;
2651 emit->temp_map[i].arrayId = arrayID;
2652 emit->temp_map[i].index = i;
2661 if (emit->unit == PIPE_SHADER_VERTEX || emit->unit == PIPE_SHADER_GEOMETRY) {
2662 if (emit->vposition.need_prescale || emit->key.vs.undo_viewport ||
2663 emit->key.clip_plane_enable ||
2664 emit->vposition.so_index != INVALID_INDEX) {
2665 emit->vposition.tmp_index = total_temps;
2669 if (emit->unit == PIPE_SHADER_VERTEX) {
2670 unsigned attrib_mask = (emit->key.vs.adjust_attrib_w_1 |
2671 emit->key.vs.adjust_attrib_itof |
2672 emit->key.vs.adjust_attrib_utof |
2673 emit->key.vs.attrib_is_bgra |
2674 emit->key.vs.attrib_puint_to_snorm |
2675 emit->key.vs.attrib_puint_to_uscaled |
2676 emit->key.vs.attrib_puint_to_sscaled);
2679 emit->vs.adjusted_input[index] = total_temps++;
2683 if (emit->clip_mode == CLIP_DISTANCE) {
2690 emit->clip_dist_tmp_index = total_temps++;
2691 if (emit->info.num_written_clipdistance > 4)
2694 else if (emit->clip_mode == CLIP_VERTEX) {
2698 assert(emit->info.writes_clipvertex > 0);
2699 emit->clip_vertex_tmp_index = total_temps;
2703 else if (emit->unit == PIPE_SHADER_FRAGMENT) {
2704 if (emit->key.fs.alpha_func != SVGA3D_CMP_ALWAYS ||
2705 emit->key.fs.white_fragments ||
2706 emit->key.fs.write_color0_to_n_cbufs > 1) {
2708 emit->fs.color_tmp_index = total_temps;
2712 if (emit->fs.face_input_index != INVALID_INDEX) {
2714 emit->fs.face_tmp_index = total_temps;
2718 if (emit->fs.fragcoord_input_index != INVALID_INDEX) {
2720 emit->fs.fragcoord_tmp_index = total_temps;
2725 for (i = 0; i < emit->num_address_regs; i++) {
2726 emit->address_reg_index[i] = total_temps++;
2754 * Any time we emit a temporary register index, we'll have to use the
2761 if (emit->temp_map[i].arrayId == 0) {
2762 emit->temp_map[i].index = reg++;
2770 i, emit->temp_map[i].arrayId, emit->temp_map[i].index);
2776 /* Emit declaration of ordinary temp registers */
2783 begin_emit_instruction(emit);
2784 emit_dword(emit, opcode0.value);
2785 emit_dword(emit, total_temps);
2786 end_emit_instruction(emit);
2789 /* Emit declarations for indexable temp arrays. Skip 0th entry since
2792 for (i = 1; i < emit->num_temp_arrays; i++) {
2793 unsigned num_temps = emit->temp_arrays[i].size;
2801 begin_emit_instruction(emit);
2802 emit_dword(emit, opcode0.value);
2803 emit_dword(emit, i); /* which array */
2804 emit_dword(emit, num_temps);
2805 emit_dword(emit, 4); /* num components */
2806 end_emit_instruction(emit);
2815 check_register_index(emit, VGPU10_OPCODE_DCL_TEMPS, total_temps - 1);
2822 emit_constant_declaration(struct svga_shader_emitter_v10 *emit)
2846 * Emit declaration for constant buffer [0]. We also allocate
2849 total_consts = emit->num_shader_consts[0];
2854 if (emit->vposition.need_prescale) {
2855 emit->vposition.prescale_scale_index = total_consts++;
2856 emit->vposition.prescale_trans_index = total_consts++;
2859 if (emit->unit == PIPE_SHADER_VERTEX) {
2860 if (emit->key.vs.undo_viewport) {
2861 emit->vs.viewport_index = total_consts++;
2866 if (emit->key.clip_plane_enable) {
2867 unsigned n = util_bitcount(emit->key.clip_plane_enable);
2868 assert(emit->unit == PIPE_SHADER_VERTEX ||
2869 emit->unit == PIPE_SHADER_GEOMETRY);
2871 emit->clip_plane_const[i] = total_consts++;
2877 for (i = 0; i < emit->num_samplers; i++) {
2878 if (emit->key.tex[i].unnormalized) {
2879 emit->texcoord_scale_index[i] = total_consts++;
2885 for (i = 0; i < emit->num_samplers; i++) {
2886 if (emit->sampler_target[i] == TGSI_TEXTURE_BUFFER) {
2887 emit->texture_buffer_size_index[i] = total_consts++;
2892 begin_emit_instruction(emit);
2893 emit_dword(emit, opcode0.value);
2894 emit_dword(emit, operand0.value);
2895 emit_dword(emit, 0); /* which const buffer slot */
2896 emit_dword(emit, total_consts);
2897 end_emit_instruction(emit);
2901 for (i = 1; i < ARRAY_SIZE(emit->num_shader_consts); i++) {
2902 if (emit->num_shader_consts[i] > 0) {
2903 begin_emit_instruction(emit);
2904 emit_dword(emit, opcode0.value);
2905 emit_dword(emit, operand0.value);
2906 emit_dword(emit, i); /* which const buffer slot */
2907 emit_dword(emit, emit->num_shader_consts[i]);
2908 end_emit_instruction(emit);
2917 * Emit declarations for samplers.
2920 emit_sampler_declarations(struct svga_shader_emitter_v10 *emit)
2924 for (i = 0; i < emit->num_samplers; i++) {
2938 begin_emit_instruction(emit);
2939 emit_dword(emit, opcode0.value);
2940 emit_dword(emit, operand0.value);
2941 emit_dword(emit, i);
2942 end_emit_instruction(emit);
3019 * Emit declarations for resources.
3025 emit_resource_declarations(struct svga_shader_emitter_v10 *emit)
3029 /* Emit resource decl for each sampler */
3030 for (i = 0; i < emit->num_samplers; i++) {
3039 tgsi_texture_to_resource_dimension(emit->sampler_target[i],
3040 emit->key.tex[i].is_array);
3054 assert(emit->sampler_return_type[i] <= TGSI_RETURN_TYPE_FLOAT);
3055 rt = emit->sampler_return_type[i] + 1;
3057 switch (emit->sampler_return_type[i]) {
3076 begin_emit_instruction(emit);
3077 emit_dword(emit, opcode0.value);
3078 emit_dword(emit, operand0.value);
3079 emit_dword(emit, i);
3080 emit_dword(emit, return_type.value);
3081 end_emit_instruction(emit);
3088 emit_instruction_op1(struct svga_shader_emitter_v10 *emit,
3094 begin_emit_instruction(emit);
3095 emit_opcode(emit, opcode, saturate);
3096 emit_dst_register(emit, dst);
3097 emit_src_register(emit, src);
3098 end_emit_instruction(emit);
3102 emit_instruction_op2(struct svga_shader_emitter_v10 *emit,
3109 begin_emit_instruction(emit);
3110 emit_opcode(emit, opcode, saturate);
3111 emit_dst_register(emit, dst);
3112 emit_src_register(emit, src1);
3113 emit_src_register(emit, src2);
3114 end_emit_instruction(emit);
3118 emit_instruction_op3(struct svga_shader_emitter_v10 *emit,
3126 begin_emit_instruction(emit);
3127 emit_opcode(emit, opcode, saturate);
3128 emit_dst_register(emit, dst);
3129 emit_src_register(emit, src1);
3130 emit_src_register(emit, src2);
3131 emit_src_register(emit, src3);
3132 end_emit_instruction(emit);
3136 * Emit the actual clip distance instructions to be used for clipping
3143 emit_clip_distance_instructions(struct svga_shader_emitter_v10 *emit)
3149 unsigned clip_plane_enable = emit->key.clip_plane_enable;
3150 unsigned clip_dist_tmp_index = emit->clip_dist_tmp_index;
3151 int num_written_clipdist = emit->info.num_written_clipdistance;
3153 assert(emit->clip_dist_out_index != INVALID_INDEX);
3154 assert(emit->clip_dist_tmp_index != INVALID_INDEX);
3161 emit->clip_dist_tmp_index = INVALID_INDEX;
3173 emit->clip_dist_so_index + i);
3176 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &clip_dist_dst,
3185 emit->clip_dist_out_index + i);
3189 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &clip_dist_dst,
3199 emit->clip_dist_tmp_index = clip_dist_tmp_index;
3206 emit_clip_distance_declarations(struct svga_shader_emitter_v10 *emit)
3208 unsigned num_clip_planes = util_bitcount(emit->key.clip_plane_enable);
3209 unsigned index = emit->num_outputs;
3212 assert(emit->unit == PIPE_SHADER_VERTEX ||
3213 emit->unit == PIPE_SHADER_GEOMETRY);
3216 if (emit->clip_mode != CLIP_LEGACY &&
3217 emit->clip_mode != CLIP_VERTEX) {
3230 emit->clip_dist_out_index = index; /* save the starting clip dist reg index */
3235 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT_SIV, index,
3237 emit->num_outputs++;
3241 emit_output_declaration(emit, VGPU10_OPCODE_DCL_OUTPUT_SIV, index + 1,
3243 emit->num_outputs++;
3249 * Emit the instructions for writing to the clip distance registers
3257 emit_clip_distance_from_vpos(struct svga_shader_emitter_v10 *emit,
3260 unsigned i, num_clip_planes = util_bitcount(emit->key.clip_plane_enable);
3262 assert(emit->clip_mode == CLIP_LEGACY);
3265 assert(emit->unit == PIPE_SHADER_VERTEX ||
3266 emit->unit == PIPE_SHADER_GEOMETRY);
3271 unsigned reg_index = emit->clip_dist_out_index + i / 4;
3279 plane_src = make_src_const_reg(emit->clip_plane_const[i]);
3283 emit_instruction_op2(emit, VGPU10_OPCODE_DP4, &dst,
3290 * Emit the instructions for computing the clip distance results from
3296 emit_clip_vertex_instructions(struct svga_shader_emitter_v10 *emit)
3298 const unsigned num_clip = util_bitcount(emit->key.clip_plane_enable);
3302 const unsigned clip_vertex_tmp = emit->clip_vertex_tmp_index;
3304 assert(emit->unit == PIPE_SHADER_VERTEX ||
3305 emit->unit == PIPE_SHADER_GEOMETRY);
3307 assert(emit->clip_mode == CLIP_VERTEX);
3313 unsigned reg_index = emit->clip_dist_out_index + i / 4;
3321 plane_src = make_src_const_reg(emit->clip_plane_const[i]);
3324 emit_instruction_op2(emit, VGPU10_OPCODE_DP4, &dst,
3330 assert(emit->clip_vertex_out_index != INVALID_INDEX);
3337 emit->clip_vertex_tmp_index = INVALID_INDEX;
3340 dst = make_dst_reg(TGSI_FILE_OUTPUT, emit->clip_vertex_out_index);
3341 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
3348 emit->clip_vertex_tmp_index = clip_vertex_tmp;
3352 * Emit code to convert RGBA to BGRA
3355 emit_swap_r_b(struct svga_shader_emitter_v10 *emit,
3362 begin_emit_instruction(emit);
3363 emit_opcode(emit, VGPU10_OPCODE_MOV, FALSE);
3364 emit_dst_register(emit, dst);
3365 emit_src_register(emit, &bgra_src);
3366 end_emit_instruction(emit);
3372 emit_puint_to_snorm(struct svga_shader_emitter_v10 *emit,
3376 struct tgsi_full_src_register half = make_immediate_reg_float(emit, 0.5f);
3378 make_immediate_reg_float4(emit, 2.0f, 2.0f, 2.0f, 3.0f);
3380 make_immediate_reg_float4(emit, -2.0f, -2.0f, -2.0f, -1.66666f);
3382 unsigned val_tmp = get_temp_index(emit);
3386 unsigned bias_tmp = get_temp_index(emit);
3391 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &val_dst,
3395 emit_instruction_op2(emit, VGPU10_OPCODE_GE, &bias_dst,
3399 emit_instruction_op2(emit, VGPU10_OPCODE_AND, &bias_dst,
3403 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, dst,
3406 free_temp_indexes(emit);
3412 emit_puint_to_uscaled(struct svga_shader_emitter_v10 *emit,
3417 make_immediate_reg_float4(emit, 1023.0f, 1023.0f, 1023.0f, 3.0f);
3420 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, dst, src, &scale, FALSE);
3426 emit_puint_to_sscaled(struct svga_shader_emitter_v10 *emit,
3431 make_immediate_reg_int4(emit, 22, 12, 2, 0);
3433 make_immediate_reg_int4(emit, 22, 22, 22, 30);
3437 unsigned tmp = get_temp_index(emit);
3448 emit_instruction_op2(emit, VGPU10_OPCODE_ISHL, &tmp_dst,
3450 emit_instruction_op2(emit, VGPU10_OPCODE_ISHR, &tmp_dst,
3452 emit_instruction_op1(emit, VGPU10_OPCODE_ITOF, dst, &tmp_src, FALSE);
3454 free_temp_indexes(emit);
3459 * Emit code for TGSI_OPCODE_ARL or TGSI_OPCODE_UARL instruction.
3462 emit_arl_uarl(struct svga_shader_emitter_v10 *emit,
3470 dst = make_dst_temp_reg(emit->address_reg_index[index]);
3485 emit_instruction_op1(emit, opcode, &dst, &inst->Src[0], FALSE);
3492 * Emit code for TGSI_OPCODE_CAL instruction.
3495 emit_cal(struct svga_shader_emitter_v10 *emit,
3503 begin_emit_instruction(emit);
3504 emit_dword(emit, operand.value);
3505 emit_dword(emit, label);
3506 end_emit_instruction(emit);
3513 * Emit code for TGSI_OPCODE_IABS instruction.
3516 emit_iabs(struct svga_shader_emitter_v10 *emit,
3528 emit_instruction_op2(emit, VGPU10_OPCODE_IMAX, &inst->Dst[0],
3536 * Emit code for TGSI_OPCODE_CMP instruction.
3539 emit_cmp(struct svga_shader_emitter_v10 *emit,
3551 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
3552 unsigned tmp = get_temp_index(emit);
3556 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp_dst,
3558 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0],
3562 free_temp_indexes(emit);
3569 * Emit code for TGSI_OPCODE_DP2A instruction.
3572 emit_dp2a(struct svga_shader_emitter_v10 *emit,
3584 unsigned tmp = get_temp_index(emit);
3604 emit_instruction_op3(emit, VGPU10_OPCODE_MAD, &tmp_dst_x, &src0_yyyy,
3606 emit_instruction_op3(emit, VGPU10_OPCODE_MAD, &tmp_dst_x, &src0_xxxx,
3608 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0],
3611 free_temp_indexes(emit);
3618 * Emit code for TGSI_OPCODE_DPH instruction.
3621 emit_dph(struct svga_shader_emitter_v10 *emit,
3633 unsigned tmp = get_temp_index(emit);
3638 emit_instruction_op2(emit, VGPU10_OPCODE_DP3, &tmp_dst, &inst->Src[0],
3642 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &inst->Dst[0], &tmp_src,
3645 free_temp_indexes(emit);
3652 * Emit code for TGSI_OPCODE_DST instruction.
3655 emit_dst(struct svga_shader_emitter_v10 *emit,
3678 unsigned tmp_move = get_temp_index(emit);
3686 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
3688 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_x, &one, FALSE);
3696 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &dst_y, &s0_yyyy,
3705 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_z, &s0_zzzz,
3714 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_w, &s1_wwww,
3718 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &move_src,
3720 free_temp_indexes(emit);
3728 * Emit code for TGSI_OPCODE_ENDPRIM (GS only)
3731 emit_endprim(struct svga_shader_emitter_v10 *emit,
3734 assert(emit->unit == PIPE_SHADER_GEOMETRY);
3739 begin_emit_instruction(emit);
3740 emit_opcode(emit, VGPU10_OPCODE_CUT, FALSE);
3741 end_emit_instruction(emit);
3747 * Emit code for TGSI_OPCODE_EX2 (2^x) instruction.
3750 emit_ex2(struct svga_shader_emitter_v10 *emit,
3765 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &inst->Dst[0], &src_xxxx,
3773 * Emit code for TGSI_OPCODE_EXP instruction.
3776 emit_exp(struct svga_shader_emitter_v10 *emit,
3788 unsigned tmp = get_temp_index(emit);
3796 unsigned tmp_move = get_temp_index(emit);
3805 emit_instruction_op1(emit, VGPU10_OPCODE_ROUND_NI, &tmp_dst,
3813 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &dst_x, &tmp_src,
3823 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &dst_y, &src_xxxx,
3832 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &dst_z, &src_xxxx,
3840 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
3842 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_w, &one,
3846 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &move_src,
3849 free_temp_indexes(emit);
3856 * Emit code for TGSI_OPCODE_IF instruction.
3859 emit_if(struct svga_shader_emitter_v10 *emit,
3877 begin_emit_instruction(emit);
3878 emit_dword(emit, opcode0.value);
3879 emit_src_register(emit, &inst->Src[0]);
3880 end_emit_instruction(emit);
3887 * Emit code for TGSI_OPCODE_KILL_IF instruction (kill fragment if any of
3891 emit_kill_if(struct svga_shader_emitter_v10 *emit,
3894 unsigned tmp = get_temp_index(emit);
3898 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
3906 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp_dst, &inst->Src[0],
3921 emit_instruction_op2(emit, VGPU10_OPCODE_OR, &tmp_dst_x, &tmp_src_xxxx,
3923 emit_instruction_op2(emit, VGPU10_OPCODE_OR, &tmp_dst_x, &tmp_src_xxxx,
3925 emit_instruction_op2(emit, VGPU10_OPCODE_OR, &tmp_dst_x, &tmp_src_xxxx,
3929 begin_emit_instruction(emit);
3930 emit_discard_opcode(emit, TRUE); /* discard if src0.x is non-zero */
3931 emit_src_register(emit, &tmp_src_xxxx);
3932 end_emit_instruction(emit);
3934 free_temp_indexes(emit);
3941 * Emit code for TGSI_OPCODE_KILL instruction (unconditional discard).
3944 emit_kill(struct svga_shader_emitter_v10 *emit,
3947 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
3950 begin_emit_instruction(emit);
3951 emit_discard_opcode(emit, FALSE);
3952 emit_src_register(emit, &zero);
3953 end_emit_instruction(emit);
3960 * Emit code for TGSI_OPCODE_LG2 instruction.
3963 emit_lg2(struct svga_shader_emitter_v10 *emit,
3978 emit_instruction_op1(emit, VGPU10_OPCODE_LOG, &inst->Dst[0], &src_xxxx,
3986 * Emit code for TGSI_OPCODE_LIT instruction.
3989 emit_lit(struct svga_shader_emitter_v10 *emit,
3992 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
3998 unsigned tmp_move = get_temp_index(emit);
4013 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_x, &one, FALSE);
4020 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_w, &one, FALSE);
4028 make_immediate_reg_float(emit, 0.0f);
4033 emit_instruction_op2(emit, VGPU10_OPCODE_MAX, &dst_y, &src_xxxx,
4062 unsigned tmp1 = get_temp_index(emit);
4065 unsigned tmp2 = get_temp_index(emit);
4077 make_immediate_reg_float(emit, 0.0f);
4079 make_immediate_reg_float(emit, -128.0f);
4081 make_immediate_reg_float(emit, 128.0f);
4083 emit_instruction_op2(emit, VGPU10_OPCODE_MAX, &tmp1_dst, &src_wwww,
4085 emit_instruction_op2(emit, VGPU10_OPCODE_MIN, &tmp1_dst, &tmp1_src,
4087 emit_instruction_op2(emit, VGPU10_OPCODE_MAX, &tmp2_dst, &src_yyyy,
4092 emit_instruction_op1(emit, VGPU10_OPCODE_LOG, &tmp2_dst, &tmp2_src,
4096 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp1_dst, &tmp2_src,
4100 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &tmp1_dst, &tmp1_src,
4104 emit_instruction_op2(emit, VGPU10_OPCODE_EQ, &tmp2_dst, &zero,
4107 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &tmp1_dst,
4111 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp2_dst, &zero,
4114 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &dst_z,
4118 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &move_src,
4120 free_temp_indexes(emit);
4127 * Emit code for TGSI_OPCODE_LOG instruction.
4130 emit_log(struct svga_shader_emitter_v10 *emit,
4142 unsigned tmp = get_temp_index(emit);
4153 emit_instruction_op1(emit, VGPU10_OPCODE_LOG, &tmp_dst,
4162 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_z,
4168 emit_instruction_op1(emit, VGPU10_OPCODE_ROUND_NI, &tmp_dst,
4177 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_x, &tmp_src,
4187 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &tmp_dst, &tmp_src,
4189 emit_instruction_op2(emit, VGPU10_OPCODE_DIV, &dst_y, &abs_src_xxxx,
4198 make_immediate_reg_float(emit, 1.0f);
4200 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst_w, &one, FALSE);
4203 free_temp_indexes(emit);
4210 * Emit code for TGSI_OPCODE_LRP instruction.
4213 emit_lrp(struct svga_shader_emitter_v10 *emit,
4222 unsigned tmp = get_temp_index(emit);
4228 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &dst_tmp,
4232 emit_instruction_op3(emit, VGPU10_OPCODE_MAD, &inst->Dst[0],
4236 free_temp_indexes(emit);
4243 * Emit code for TGSI_OPCODE_POW instruction.
4246 emit_pow(struct svga_shader_emitter_v10 *emit,
4255 unsigned tmp = get_temp_index(emit);
4266 emit_instruction_op1(emit, VGPU10_OPCODE_LOG, &tmp_dst, &src0_xxxx,
4270 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_dst, &tmp_src,
4274 emit_instruction_op1(emit, VGPU10_OPCODE_EXP, &inst->Dst[0],
4278 free_temp_indexes(emit);
4285 * Emit code for TGSI_OPCODE_RCP (reciprocal) instruction.
4288 emit_rcp(struct svga_shader_emitter_v10 *emit,
4291 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4293 unsigned tmp = get_temp_index(emit);
4303 emit_instruction_op2(emit, VGPU10_OPCODE_DIV, &tmp_dst_x, &one,
4307 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0],
4310 free_temp_indexes(emit);
4317 * Emit code for TGSI_OPCODE_RSQ instruction.
4320 emit_rsq(struct svga_shader_emitter_v10 *emit,
4330 unsigned tmp = get_temp_index(emit);
4340 emit_instruction_op1(emit, VGPU10_OPCODE_RSQ, &tmp_dst_x,
4344 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0],
4348 free_temp_indexes(emit);
4355 * Emit code for TGSI_OPCODE_SCS instruction.
4358 emit_scs(struct svga_shader_emitter_v10 *emit,
4374 make_immediate_reg_float4(emit, 0.0f, 0.0f, 0.0f, 1.0f);
4376 begin_emit_instruction(emit);
4377 emit_opcode(emit, VGPU10_OPCODE_SINCOS, inst->Instruction.Saturate);
4378 emit_dst_register(emit, &dst_y);
4379 emit_dst_register(emit, &dst_x);
4380 emit_src_register(emit, &inst->Src[0]);
4381 end_emit_instruction(emit);
4383 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
4391 * Emit code for TGSI_OPCODE_SEQ (Set Equal) instruction.
4394 emit_seq(struct svga_shader_emitter_v10 *emit,
4403 unsigned tmp = get_temp_index(emit);
4406 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4407 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4410 emit_instruction_op2(emit, VGPU10_OPCODE_EQ, &tmp_dst, &inst->Src[0],
4414 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4417 free_temp_indexes(emit);
4424 * Emit code for TGSI_OPCODE_SGE (Set Greater than or Equal) instruction.
4427 emit_sge(struct svga_shader_emitter_v10 *emit,
4436 unsigned tmp = get_temp_index(emit);
4439 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4440 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4443 emit_instruction_op2(emit, VGPU10_OPCODE_GE, &tmp_dst, &inst->Src[0],
4447 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4450 free_temp_indexes(emit);
4457 * Emit code for TGSI_OPCODE_SGT (Set Greater than) instruction.
4460 emit_sgt(struct svga_shader_emitter_v10 *emit,
4469 unsigned tmp = get_temp_index(emit);
4472 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4473 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4476 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp_dst, &inst->Src[1],
4480 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4483 free_temp_indexes(emit);
4490 * Emit code for TGSI_OPCODE_SIN and TGSI_OPCODE_COS instructions.
4493 emit_sincos(struct svga_shader_emitter_v10 *emit,
4496 unsigned tmp = get_temp_index(emit);
4505 begin_emit_instruction(emit);
4506 emit_opcode(emit, VGPU10_OPCODE_SINCOS, FALSE);
4510 emit_dst_register(emit, &tmp_dst_x); /* first destination register */
4511 emit_null_dst_register(emit); /* second destination register */
4514 emit_null_dst_register(emit);
4515 emit_dst_register(emit, &tmp_dst_x);
4518 emit_src_register(emit, &inst->Src[0]);
4519 end_emit_instruction(emit);
4521 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0],
4524 free_temp_indexes(emit);
4531 * Emit code for TGSI_OPCODE_SLE (Set Less than or Equal) instruction.
4534 emit_sle(struct svga_shader_emitter_v10 *emit,
4543 unsigned tmp = get_temp_index(emit);
4546 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4547 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4550 emit_instruction_op2(emit, VGPU10_OPCODE_GE, &tmp_dst, &inst->Src[1],
4554 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4557 free_temp_indexes(emit);
4564 * Emit code for TGSI_OPCODE_SLT (Set Less than) instruction.
4567 emit_slt(struct svga_shader_emitter_v10 *emit,
4576 unsigned tmp = get_temp_index(emit);
4579 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4580 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4583 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp_dst, &inst->Src[0],
4587 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4590 free_temp_indexes(emit);
4597 * Emit code for TGSI_OPCODE_SNE (Set Not Equal) instruction.
4600 emit_sne(struct svga_shader_emitter_v10 *emit,
4609 unsigned tmp = get_temp_index(emit);
4612 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4613 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
4616 emit_instruction_op2(emit, VGPU10_OPCODE_NE, &tmp_dst, &inst->Src[0],
4620 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp_src,
4623 free_temp_indexes(emit);
4630 * Emit code for TGSI_OPCODE_SSG (Set Sign) instruction.
4633 emit_ssg(struct svga_shader_emitter_v10 *emit,
4647 make_immediate_reg_float(emit, 0.0f);
4649 make_immediate_reg_float(emit, 1.0f);
4651 make_immediate_reg_float(emit, -1.0f);
4653 unsigned tmp1 = get_temp_index(emit);
4657 unsigned tmp2 = get_temp_index(emit);
4661 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp1_dst, &inst->Src[0],
4663 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &tmp2_dst, &tmp1_src,
4665 emit_instruction_op2(emit, VGPU10_OPCODE_LT, &tmp1_dst, &zero,
4667 emit_instruction_op3(emit, VGPU10_OPCODE_MOVC, &inst->Dst[0], &tmp1_src,
4670 free_temp_indexes(emit);
4677 * Emit code for TGSI_OPCODE_ISSG (Integer Set Sign) instruction.
4680 emit_issg(struct svga_shader_emitter_v10 *emit,
4692 struct tgsi_full_src_register zero = make_immediate_reg_float(emit, 0.0f);
4694 unsigned tmp1 = get_temp_index(emit);
4698 unsigned tmp2 = get_temp_index(emit);
4704 emit_instruction_op2(emit, VGPU10_OPCODE_ILT, &tmp1_dst,
4706 emit_instruction_op2(emit, VGPU10_OPCODE_ILT, &tmp2_dst,
4708 emit_instruction_op2(emit, VGPU10_OPCODE_IADD, &inst->Dst[0],
4711 free_temp_indexes(emit);
4718 * Emit a comparison instruction. The dest register will get
4722 emit_comparison(struct svga_shader_emitter_v10 *emit,
4740 immediate = make_immediate_reg_int(emit, 0);
4742 begin_emit_instruction(emit);
4743 emit_dword(emit, VGPU10_OPCODE_MOV);
4744 emit_dst_register(emit, dst);
4745 emit_src_register(emit, &immediate);
4746 end_emit_instruction(emit);
4749 immediate = make_immediate_reg_int(emit, -1);
4751 begin_emit_instruction(emit);
4752 emit_dword(emit, VGPU10_OPCODE_MOV);
4753 emit_dst_register(emit, dst);
4754 emit_src_register(emit, &immediate);
4755 end_emit_instruction(emit);
4782 begin_emit_instruction(emit);
4783 emit_dword(emit, opcode0.value);
4784 emit_dst_register(emit, dst);
4786 emit_src_register(emit, src1);
4787 emit_src_register(emit, src0);
4790 emit_src_register(emit, src0);
4791 emit_src_register(emit, src1);
4793 end_emit_instruction(emit);
4801 get_texel_offsets(const struct svga_shader_emitter_v10 *emit,
4813 const union tgsi_immediate_data *imm = emit->immediates[index];
4836 setup_texcoord(struct svga_shader_emitter_v10 *emit,
4840 if (emit->key.tex[unit].unnormalized) {
4841 unsigned scale_index = emit->texcoord_scale_index[unit];
4842 unsigned tmp = get_temp_index(emit);
4848 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_dst,
4860 * For SAMPLE_C instructions, emit the extra src register which indicates
4864 emit_tex_compare_refcoord(struct svga_shader_emitter_v10 *emit,
4882 emit_src_register(emit, &coord_src_ref);
4915 begin_tex_swizzle(struct svga_shader_emitter_v10 *emit,
4921 swz->swizzled = (emit->key.tex[unit].swizzle_r != TGSI_SWIZZLE_X ||
4922 emit->key.tex[unit].swizzle_g != TGSI_SWIZZLE_Y ||
4923 emit->key.tex[unit].swizzle_b != TGSI_SWIZZLE_Z ||
4924 emit->key.tex[unit].swizzle_a != TGSI_SWIZZLE_W);
4933 unsigned tmp = get_temp_index(emit);
4962 end_tex_swizzle(struct svga_shader_emitter_v10 *emit,
4966 /* Emit extra instructions to compare the fetched texel value against
4974 make_immediate_reg_float(emit, 1.0f);
4976 SVGA3dCmpFunc compare_func = emit->key.tex[swz->unit].compare_func + 1;
4978 assert(emit->unit == PIPE_SHADER_FRAGMENT);
5002 emit_comparison(emit, compare_func,
5006 begin_emit_instruction(emit);
5007 emit_opcode(emit, VGPU10_OPCODE_AND, FALSE);
5009 emit_dst_register(emit, &swz->tmp_dst);
5012 emit_dst_register(emit, swz->inst_dst);
5014 emit_src_register(emit, &swz->tmp_src);
5015 emit_src_register(emit, &one);
5016 end_emit_instruction(emit);
5020 unsigned swz_r = emit->key.tex[swz->unit].swizzle_r;
5021 unsigned swz_g = emit->key.tex[swz->unit].swizzle_g;
5022 unsigned swz_b = emit->key.tex[swz->unit].swizzle_b;
5023 unsigned swz_a = emit->key.tex[swz->unit].swizzle_a;
5025 boolean int_tex = is_integer_type(emit->sampler_return_type[swz->unit]);
5036 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
5047 make_immediate_reg_int(emit, 0) :
5048 make_immediate_reg_float(emit, 0.0f);
5053 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
5065 make_immediate_reg_int(emit, 1) :
5066 make_immediate_reg_float(emit, 1.0f);
5071 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &dst, &one, FALSE);
5078 * Emit code for TGSI_OPCODE_SAMPLE instruction.
5081 emit_sample(struct svga_shader_emitter_v10 *emit,
5090 begin_tex_swizzle(emit, sampler_unit, inst, FALSE, &swz_info);
5092 get_texel_offsets(emit, inst, offsets);
5094 coord = setup_texcoord(emit, resource_unit, &inst->Src[0]);
5097 begin_emit_instruction(emit);
5099 emit_sample_opcode(emit, VGPU10_OPCODE_SAMPLE,
5101 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5102 emit_src_register(emit, &coord);
5103 emit_resource_register(emit, resource_unit);
5104 emit_sampler_register(emit, sampler_unit);
5105 end_emit_instruction(emit);
5107 end_tex_swizzle(emit, &swz_info);
5109 free_temp_indexes(emit);
5124 is_valid_tex_instruction(struct svga_shader_emitter_v10 *emit,
5132 is_integer_type(emit->sampler_return_type[unit])) {
5139 /* emit a MOV dst, {1,1,1,1} instruction. */
5140 struct tgsi_full_src_register one = make_immediate_reg_float(emit, 1.0f);
5141 begin_emit_instruction(emit);
5142 emit_opcode(emit, VGPU10_OPCODE_MOV, FALSE);
5143 emit_dst_register(emit, &inst->Dst[0]);
5144 emit_src_register(emit, &one);
5145 end_emit_instruction(emit);
5153 * Emit code for TGSI_OPCODE_TEX (simple texture lookup)
5156 emit_tex(struct svga_shader_emitter_v10 *emit,
5167 if (!is_valid_tex_instruction(emit, inst))
5170 begin_tex_swizzle(emit, unit, inst, FALSE, &swz_info);
5172 get_texel_offsets(emit, inst, offsets);
5174 coord = setup_texcoord(emit, unit, &inst->Src[0]);
5177 begin_emit_instruction(emit);
5184 emit_sample_opcode(emit, opcode, inst->Instruction.Saturate, offsets);
5185 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5186 emit_src_register(emit, &coord);
5187 emit_resource_register(emit, unit);
5188 emit_sampler_register(emit, unit);
5190 emit_tex_compare_refcoord(emit, target, &coord);
5192 end_emit_instruction(emit);
5194 end_tex_swizzle(emit, &swz_info);
5196 free_temp_indexes(emit);
5203 * Emit code for TGSI_OPCODE_TXP (projective texture)
5206 emit_txp(struct svga_shader_emitter_v10 *emit,
5213 unsigned tmp = get_temp_index(emit);
5222 if (!is_valid_tex_instruction(emit, inst))
5225 begin_tex_swizzle(emit, unit, inst, FALSE, &swz_info);
5227 get_texel_offsets(emit, inst, offsets);
5229 coord = setup_texcoord(emit, unit, &inst->Src[0]);
5232 emit_instruction_op2(emit, VGPU10_OPCODE_DIV, &tmp_dst,
5236 begin_emit_instruction(emit);
5243 emit_sample_opcode(emit, opcode, inst->Instruction.Saturate, offsets);
5244 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5245 emit_src_register(emit, &tmp_src); /* projected coord */
5246 emit_resource_register(emit, unit);
5247 emit_sampler_register(emit, unit);
5249 emit_tex_compare_refcoord(emit, target, &tmp_src);
5251 end_emit_instruction(emit);
5253 end_tex_swizzle(emit, &swz_info);
5255 free_temp_indexes(emit);
5262 * Emit code for TGSI_OPCODE_XPD instruction.
5265 emit_xpd(struct svga_shader_emitter_v10 *emit,
5287 unsigned tmp1 = get_temp_index(emit);
5291 unsigned tmp2 = get_temp_index(emit);
5296 unsigned tmp3 = get_temp_index(emit);
5321 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp1_dst,
5323 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp2_dst,
5325 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &tmp3_dst_x,
5333 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp1_dst, &s0_zzzz,
5335 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp2_dst, &s1_zzzz,
5337 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &tmp3_dst_y,
5345 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp1_dst, &s0_xxxx,
5347 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp2_dst, &s1_xxxx,
5349 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &tmp3_dst_z,
5356 make_immediate_reg_float(emit, 1.0f);
5358 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &tmp3_dst_w, &one, FALSE);
5362 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &tmp3_src,
5366 free_temp_indexes(emit);
5373 * Emit code for TGSI_OPCODE_TXD (explicit derivatives)
5376 emit_txd(struct svga_shader_emitter_v10 *emit,
5385 begin_tex_swizzle(emit, unit, inst, tgsi_is_shadow_target(target),
5388 get_texel_offsets(emit, inst, offsets);
5390 coord = setup_texcoord(emit, unit, &inst->Src[0]);
5393 begin_emit_instruction(emit);
5394 emit_sample_opcode(emit, VGPU10_OPCODE_SAMPLE_D,
5396 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5397 emit_src_register(emit, &coord);
5398 emit_resource_register(emit, unit);
5399 emit_sampler_register(emit, unit);
5400 emit_src_register(emit, &inst->Src[1]); /* Xderiv */
5401 emit_src_register(emit, &inst->Src[2]); /* Yderiv */
5402 end_emit_instruction(emit);
5404 end_tex_swizzle(emit, &swz_info);
5406 free_temp_indexes(emit);
5413 * Emit code for TGSI_OPCODE_TXF (texel fetch)
5416 emit_txf(struct svga_shader_emitter_v10 *emit,
5424 begin_tex_swizzle(emit, unit, inst, FALSE, &swz_info);
5426 get_texel_offsets(emit, inst, offsets);
5433 begin_emit_instruction(emit);
5434 emit_sample_opcode(emit, VGPU10_OPCODE_LD_MS,
5436 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5437 emit_src_register(emit, &inst->Src[0]);
5438 emit_resource_register(emit, unit);
5439 emit_src_register(emit, &sampleIndex);
5440 end_emit_instruction(emit);
5445 begin_emit_instruction(emit);
5446 emit_sample_opcode(emit, VGPU10_OPCODE_LD,
5448 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5449 emit_src_register(emit, &inst->Src[0]);
5450 emit_resource_register(emit, unit);
5451 end_emit_instruction(emit);
5454 end_tex_swizzle(emit, &swz_info);
5456 free_temp_indexes(emit);
5463 * Emit code for TGSI_OPCODE_TXL (explicit LOD) or TGSI_OPCODE_TXB (LOD bias)
5467 emit_txl_txb(struct svga_shader_emitter_v10 *emit,
5489 begin_tex_swizzle(emit, unit, inst, tgsi_is_shadow_target(target),
5492 get_texel_offsets(emit, inst, offsets);
5494 coord = setup_texcoord(emit, unit, &inst->Src[0]);
5497 begin_emit_instruction(emit);
5504 emit_sample_opcode(emit, opcode, inst->Instruction.Saturate, offsets);
5505 emit_dst_register(emit, get_tex_swizzle_dst(&swz_info));
5506 emit_src_register(emit
5507 emit_resource_register(emit, unit);
5508 emit_sampler_register(emit, unit);
5509 emit_src_register(emit, &lod_bias);
5510 end_emit_instruction(emit);
5512 end_tex_swizzle(emit, &swz_info);
5514 free_temp_indexes(emit);
5521 * Emit code for TGSI_OPCODE_TXQ (texture query) instruction.
5524 emit_txq(struct svga_shader_emitter_v10 *emit,
5529 if (emit->sampler_target[unit] == TGSI_TEXTURE_BUFFER) {
5536 make_src_const_reg(emit->texture_buffer_size_index[unit]);
5537 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &inst->Dst[0], &size_src,
5541 begin_emit_instruction(emit);
5542 emit_opcode_resinfo(emit, VGPU10_RESINFO_RETURN_UINT);
5543 emit_dst_register(emit, &inst->Dst[0]);
5544 emit_src_register(emit, &inst->Src[0]);
5545 emit_resource_register(emit, unit);
5546 end_emit_instruction(emit);
5549 free_temp_indexes(emit);
5556 * Emit a simple instruction (like ADD, MUL, MIN, etc).
5559 emit_simple(struct svga_shader_emitter_v10 *emit,
5566 begin_emit_instruction(emit);
5567 emit_opcode(emit, translate_opcode(inst->Instruction.Opcode),
5570 emit_dst_register(emit, &inst->Dst[i]);
5573 emit_src_register(emit, &inst->Src[i]);
5575 end_emit_instruction(emit);
5586 emit_mov(struct svga_shader_emitter_v10 *emit,
5592 if (emit->unit == PIPE_SHADER_FRAGMENT &&
5597 emit->constant_color_output = TRUE;
5600 return emit_simple(emit, inst);
5605 * Emit a simple VGPU10 instruction which writes to multiple dest registers,
5609 emit_simple_1dst(struct svga_shader_emitter_v10 *emit,
5618 begin_emit_instruction(emit);
5619 emit_opcode(emit, translate_opcode(inst->Instruction.Opcode),
5624 emit_dst_register(emit, &inst->Dst[0]);
5626 emit_null_dst_register(emit);
5631 emit_src_register(emit, &inst->Src[i]);
5633 end_emit_instruction(emit);
5643 emit_vgpu10_instruction(struct svga_shader_emitter_v10 *emit,
5706 return emit_simple(emit, inst);
5709 return emit_mov(emit, inst);
5711 return emit_vertex(emit, inst);
5713 return emit_endprim(emit, inst);
5715 return emit_iabs(emit, inst);
5719 return emit_arl_uarl(emit, inst);
5724 return emit_cal(emit, inst);
5726 return emit_cmp(emit, inst);
5728 return emit_sincos(emit, inst);
5730 return emit_dp2a(emit, inst);
5732 return emit_dph(emit, inst);
5734 return emit_dst(emit, inst);
5736 return emit_ex2(emit, inst);
5738 return emit_exp(emit, inst);
5740 return emit_if(emit, inst);
5742 return emit_kill(emit, inst);
5744 return emit_kill_if(emit, inst);
5746 return emit_lg2(emit, inst);
5748 return emit_lit(emit, inst);
5750 return emit_log(emit, inst);
5752 return emit_lrp(emit, inst);
5754 return emit_pow(emit, inst);
5756 return emit_rcp(emit, inst);
5758 return emit_rsq(emit, inst);
5760 return emit_sample(emit, inst);
5762 return emit_scs(emit, inst);
5764 return emit_seq(emit, inst);
5766 return emit_sge(emit, inst);
5768 return emit_sgt(emit, inst);
5770 return emit_sincos(emit, inst);
5772 return emit_sle(emit, inst);
5774 return emit_slt(emit, inst);
5776 return emit_sne(emit, inst);
5778 return emit_ssg(emit, inst);
5780 return emit_issg(emit, inst);
5782 return emit_tex(emit, inst);
5784 return emit_txp(emit, inst);
5788 return emit_txl_txb(emit, inst);
5790 return emit_txd(emit, inst);
5792 return emit_txf(emit, inst);
5794 return emit_txq(emit, inst);
5796 return emit_if(emit, inst);
5798 return emit_xpd(emit, inst);
5804 return emit_simple_1dst(emit, inst, 2, 0);
5809 return emit_simple_1dst(emit, inst, 2, 1);
5811 if (!emit_post_helpers(emit))
5813 return emit_simple(emit, inst);
5826 * Emit the extra instructions to adjust the vertex position.
5834 emit_vpos_instructions(struct svga_shader_emitter_v10 *emit,
5840 /* Don't bother to emit any extra vertex instructions if vertex position is
5843 if (emit->vposition.out_index == INVALID_INDEX)
5847 pos_dst = make_dst_output_reg(emit->vposition.out_index);
5854 if (emit->vposition.so_index != INVALID_INDEX) {
5856 make_dst_output_reg(emit->vposition.so_index);
5859 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &pos_so_dst,
5863 if (emit->vposition.need_prescale) {
5881 make_src_const_reg(emit->vposition.prescale_scale_index);
5883 make_src_const_reg(emit->vposition.prescale_trans_index);
5886 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_pos_dst_xyz,
5890 emit_instruction_op3(emit, VGPU10_OPCODE_MAD, &pos_dst, &tmp_pos_src_w,
5893 else if (emit->key.vs.undo_viewport) {
5919 make_src_const_reg(emit->vs.viewport_index);
5925 emit_instruction_op2(emit, VGPU10_OPCODE_ADD, &tmp_pos_dst_xy,
5929 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &tmp_pos_dst_xy,
5933 emit_instruction_op2(emit, VGPU10_OPCODE_MUL, &pos_dst_xyz,
5937 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &pos_dst_w,
5947 make_dst_output_reg(emit->vposition.out_index);
5950 begin_emit_instruction(emit);
5951 emit_opcode(emit, VGPU10_OPCODE_MOV, FALSE);
5952 emit_dst_register(emit, &pos_dst);
5953 emit_src_register(emit, &tmp_pos_src);
5954 end_emit_instruction(emit);
5959 emit_clipping_instructions(struct svga_shader_emitter_v10 *emit)
5961 if (emit->clip_mode == CLIP_DISTANCE) {
5963 emit_clip_distance_instructions(emit);
5965 } else if (emit->clip_mode == CLIP_VERTEX) {
5967 emit_clip_vertex_instructions(emit);
5971 * Emit vertex position and take care of legacy user planes only if
5975 * this case, don't bother to emit more vertex instructions.
5977 if (emit->vposition.out_index == INVALID_INDEX)
5981 * Emit per-vertex clipping instructions for legacy user defined clip planes.
5982 * NOTE: we must emit the clip distance instructions before the
5986 if (emit->clip_mode == CLIP_LEGACY) {
5987 /* Emit CLIPDIST for legacy user defined clip planes */
5988 emit_clip_distance_from_vpos(emit, emit->vposition.tmp_index);
5994 * Emit extra per-vertex instructions. This includes clip-coordinate
5996 * each GS emit-vertex instruction and at the end of VS translation.
5999 emit_vertex_instructions(struct svga_shader_emitter_v10 *emit)
6001 const unsigned vs_pos_tmp_index = emit->vposition.tmp_index;
6003 /* Emit clipping instructions based on clipping mode */
6004 emit_clipping_instructions(emit);
6010 emit->vposition.tmp_index = INVALID_INDEX;
6012 /* Emit vertex position instructions */
6013 emit_vpos_instructions(emit, vs_pos_tmp_index);
6018 emit->vposition.tmp_index = vs_pos_tmp_index;
6025 emit_vertex(struct svga_shader_emitter_v10 *emit,
6030 assert(emit->unit == PIPE_SHADER_GEOMETRY);
6032 emit_vertex_instructions(emit);
6037 begin_emit_instruction(emit);
6038 emit_opcode(emit, VGPU10_OPCODE_EMIT, FALSE);
6039 end_emit_instruction(emit);
6046 * Emit the extra code to convert from VGPU10's boolean front-face
6052 emit_frontface_instructions(struct svga_shader_emitter_v10 *emit)
6054 assert(emit->unit == PIPE_SHADER_FRAGMENT);
6056 if (emit->fs.face_input_index != INVALID_INDEX) {
6059 make_dst_temp_reg(emit->fs.face_tmp_index);
6061 make_immediate_reg_float(emit, 1.0f);
6063 make_immediate_reg_float(emit, -1.0f);
6066 begin_emit_instruction(emit);
6067 emit_opcode(emit, VGPU10_OPCODE_MOVC, FALSE);
6068 emit_dst_register(emit, &tmp_dst);
6069 emit_face_register(emit);
6070 emit_src_register(emit, &one);
6071 emit_src_register(emit, &neg_one);
6072 end_emit_instruction(emit);
6078 * Emit the extra code to convert from VGPU10's fragcoord.w value to 1/w.
6081 emit_fragcoord_instructions(struct svga_shader_emitter_v10 *emit)
6083 assert(emit->unit == PIPE_SHADER_FRAGMENT);
6085 if (emit->fs.fragcoord_input_index != INVALID_INDEX) {
6087 make_dst_temp_reg(emit->fs.fragcoord_tmp_index);
6093 make_immediate_reg_float(emit, 1.0f);
6095 make_src_reg(TGSI_FILE_INPUT, emit->fs.fragcoord_input_index);
6098 unsigned fragcoord_input_index = emit->fs.fragcoord_input_index;
6100 emit->fs.fragcoord_input_index = INVALID_INDEX;
6103 begin_emit_instruction(emit);
6104 emit_opcode(emit, VGPU10_OPCODE_MOV, FALSE);
6105 emit_dst_register(emit, &tmp_dst_xyz);
6106 emit_src_register(emit, &fragcoord);
6107 end_emit_instruction(emit);
6110 begin_emit_instruction(emit);
6111 emit_opcode(emit, VGPU10_OPCODE_DIV, FALSE);
6112 emit_dst_register(emit, &tmp_dst_w);
6113 emit_src_register(emit, &one);
6114 emit_src_register(emit, &fragcoord);
6115 end_emit_instruction(emit);
6118 emit->fs.fragcoord_input_index = fragcoord_input_index;
6124 * Emit extra instructions to adjust VS inputs/attributes. This can
6129 emit_vertex_attrib_instructions(struct svga_shader_emitter_v10 *emit)
6131 const unsigned save_w_1_mask = emit->key.vs.adjust_attrib_w_1;
6132 const unsigned save_itof_mask = emit->key.vs.adjust_attrib_itof;
6133 const unsigned save_utof_mask = emit->key.vs.adjust_attrib_utof;
6134 const unsigned save_is_bgra_mask = emit->key.vs.attrib_is_bgra;
6135 const unsigned save_puint_to_snorm_mask = emit->key.vs.attrib_puint_to_snorm;
6136 const unsigned save_puint_to_uscaled_mask = emit->key.vs.attrib_puint_to_uscaled;
6137 const unsigned save_puint_to_sscaled_mask = emit->key.vs.attrib_puint_to_sscaled;
6147 assert(emit->unit == PIPE_SHADER_VERTEX);
6151 make_immediate_reg_float(emit, 1.0f);
6154 make_immediate_reg_int(emit, 1);
6159 emit->key.vs.adjust_attrib_w_1 = 0;
6160 emit->key.vs.adjust_attrib_itof = 0;
6161 emit->key.vs.adjust_attrib_utof = 0;
6162 emit->key.vs.attrib_is_bgra = 0;
6163 emit->key.vs.attrib_puint_to_snorm = 0;
6164 emit->key.vs.attrib_puint_to_uscaled = 0;
6165 emit->key.vs.attrib_puint_to_sscaled = 0;
6171 if (emit->info.input_usage_mask[index] == 0)
6174 unsigned tmp = emit->vs.adjusted_input[index];
6185 emit_instruction_op1(emit, VGPU10_OPCODE_ITOF,
6189 emit_instruction_op1(emit, VGPU10_OPCODE_UTOF,
6193 emit_puint_to_snorm(emit, &tmp_dst, &input_src);
6196 emit_puint_to_uscaled(emit, &tmp_dst, &input_src);
6199 emit_puint_to_sscaled(emit, &tmp_dst, &input_src);
6203 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
6208 emit_swap_r_b(emit, &tmp_dst, &tmp_src);
6213 if (emit->key.vs.attrib_is_pure_int & (1 << index)) {
6214 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
6218 emit_instruction_op1(emit, VGPU10_OPCODE_MOV,
6224 emit->key.vs.adjust_attrib_w_1 = save_w_1_mask;
6225 emit->key.vs.adjust_attrib_itof = save_itof_mask;
6226 emit->key.vs.adjust_attrib_utof = save_utof_mask;
6227 emit->key.vs.attrib_is_bgra = save_is_bgra_mask;
6228 emit->key.vs.attrib_puint_to_snorm = save_puint_to_snorm_mask;
6229 emit->key.vs.attrib_puint_to_uscaled = save_puint_to_uscaled_mask;
6230 emit->key.vs.attrib_puint_to_sscaled = save_puint_to_sscaled_mask;
6241 alloc_common_immediates(struct svga_shader_emitter_v10 *emit)
6245 emit->common_immediate_pos[n++] =
6246 alloc_immediate_float4(emit, 0.0f, 1.0f, 0.5f, -1.0f);
6248 emit->common_immediate_pos[n++] =
6249 alloc_immediate_float4(emit, 128.0f, -128.0f, 2.0f, 3.0f);
6251 emit->common_immediate_pos[n++] =
6252 alloc_immediate_int4(emit, 0, 1, 0, -1);
6254 if (emit->key.vs.attrib_puint_to_snorm) {
6255 emit->common_immediate_pos[n++] =
6256 alloc_immediate_float4(emit, -2.0f, -2.0f, -2.0f, -1.66666f);
6259 if (emit->key.vs.attrib_puint_to_uscaled) {
6260 emit->common_immediate_pos[n++] =
6261 alloc_immediate_float4(emit, 1023.0f, 3.0f, 0.0f, 0.0f);
6264 if (emit->key.vs.attrib_puint_to_sscaled) {
6265 emit->common_immediate_pos[n++] =
6266 alloc_immediate_int4(emit, 22, 12, 2, 0);
6268 emit->common_immediate_pos[n++] =
6269 alloc_immediate_int4(emit, 22, 30, 0, 0);
6272 assert(n <= ARRAY_SIZE(emit->common_immediate_pos));
6273 emit->num_common_immediates = n;
6278 * Emit any extra/helper declarations/code that we might need between
6282 emit_pre_helpers(struct svga_shader_emitter_v10 *emit)
6285 if (emit->unit == PIPE_SHADER_GEOMETRY)
6286 emit_property_instructions(emit);
6289 if (!emit_input_declarations(emit))
6293 if (!emit_output_declarations(emit))
6297 emit_temporaries_declaration(emit);
6300 emit_constant_declaration(emit);
6303 emit_sampler_declarations(emit);
6304 emit_resource_declarations(emit);
6307 if (emit->unit == PIPE_SHADER_VERTEX ||
6308 emit->unit == PIPE_SHADER_GEOMETRY) {
6309 emit_clip_distance_declarations(emit);
6312 alloc_common_immediates(emit);
6314 if (emit->unit == PIPE_SHADER_FRAGMENT &&
6315 emit->key.fs.alpha_func != SVGA3D_CMP_ALWAYS) {
6316 float alpha = emit->key.fs.alpha_ref;
6317 emit->fs.alpha_ref_index =
6318 alloc_immediate_float4(emit, alpha, alpha, alpha, alpha);
6321 /* Now, emit the constant block containing all the immediates
6324 emit_vgpu10_immediates_block(emit);
6326 if (emit->unit == PIPE_SHADER_FRAGMENT) {
6327 emit_frontface_instructions(emit);
6328 emit_fragcoord_instructions(emit);
6330 else if (emit->unit == PIPE_SHADER_VERTEX) {
6331 emit_vertex_attrib_instructions(emit);
6339 * Emit alpha test code. This compares TEMP[fs_color_tmp_index].w
6344 emit_alpha_test_instructions(struct svga_shader_emitter_v10 *emit,
6348 unsigned tmp = get_temp_index(emit);
6358 make_src_immediate_reg(emit->fs.alpha_ref_index);
6360 make_dst_output_reg(emit->fs.color_out_index[0]);
6362 assert(emit->unit == PIPE_SHADER_FRAGMENT);
6365 emit_comparison(emit, emit->key.fs.alpha_func, &tmp_dst,
6369 begin_emit_instruction(emit);
6370 emit_discard_opcode(emit, FALSE); /* discard if src0.x is zero */
6371 emit_src_register(emit, &tmp_src_x);
6372 end_emit_instruction(emit);
6375 * white, emit final color here.
6377 if (emit->key.fs.write_color0_to_n_cbufs <= 1 &&
6378 !emit->key.fs.white_fragments) {
6380 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &color_dst,
6384 free_temp_indexes(emit);
6389 * When we need to emit white for all fragments (for emulating XOR logicop
6393 emit_set_color_white(struct svga_shader_emitter_v10 *emit,
6399 make_immediate_reg_float(emit, 1.0f);
6401 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &color_dst, &white, FALSE);
6406 * Emit instructions for writing a single color output to multiple
6415 emit_broadcast_color_instructions(struct svga_shader_emitter_v10 *emit,
6418 const unsigned n = emit->key.fs.write_color0_to_n_cbufs;
6423 assert(emit->unit == PIPE_SHADER_FRAGMENT);
6426 unsigned output_reg = emit->fs.color_out_index[i];
6433 emit->info.output_semantic_name[output_reg] = TGSI_SEMANTIC_COLOR;
6436 emit_instruction_op1(emit, VGPU10_OPCODE_MOV, &color_dst,
6443 * Emit extra helper code after the original shader code, but before the
6449 emit_post_helpers(struct svga_shader_emitter_v10 *emit)
6451 if (emit->unit == PIPE_SHADER_VERTEX) {
6452 emit_vertex_instructions(emit);
6454 else if (emit->unit == PIPE_SHADER_FRAGMENT) {
6455 const unsigned fs_color_tmp_index = emit->fs.color_tmp_index;
6460 emit->fs.color_tmp_index = INVALID_INDEX;
6462 if (emit->key.fs.alpha_func != SVGA3D_CMP_ALWAYS) {
6463 emit_alpha_test_instructions(emit, fs_color_tmp_index);
6465 if (emit->key.fs.white_fragments) {
6466 emit_set_color_white(emit, fs_color_tmp_index);
6468 if (emit->key.fs.write_color0_to_n_cbufs > 1 ||
6469 emit->key.fs.white_fragments) {
6470 emit_broadcast_color_instructions(emit, fs_color_tmp_index);
6482 emit_vgpu10_instructions(struct svga_shader_emitter_v10 *emit,
6497 ret = emit_vgpu10_immediate(emit
6503 ret = emit_vgpu10_declaration(emit, &parse.FullToken.FullDeclaration);
6510 ret = emit_pre_helpers(emit);
6515 ret = emit_vgpu10_instruction(emit, inst_number++,
6522 ret = emit_vgpu10_property(emit, &parse.FullToken.FullProperty);
6539 * Emit the first VGPU10 shader tokens.
6542 emit_vgpu10_header(struct svga_shader_emitter_v10 *emit)
6549 ptoken.programType = translate_shader_type(emit->unit);
6550 if (!emit_dword(emit, ptoken.value))
6554 * in until we're all done. Emit zero for now.
6556 return emit_dword(emit, 0);
6561 emit_vgpu10_tail(struct svga_shader_emitter_v10 *emit)
6566 tokens = (VGPU10ProgramToken *) emit->buf;
6567 tokens[1].value = emit_get_num_tokens(emit);
6597 transform_fs_pstipple(struct svga_shader_emitter_v10 *emit,
6611 emit->fs.pstipple_sampler_unit = unit;
6614 emit->sampler_target[unit] = TGSI_TEXTURE_2D;
6615 emit->key.tex[unit].swizzle_r = TGSI_SWIZZLE_X;
6616 emit->key.tex[unit].swizzle_g = TGSI_SWIZZLE_Y;
6617 emit->key.tex[unit].swizzle_b = TGSI_SWIZZLE_Z;
6618 emit->key.tex[unit].swizzle_a = TGSI_SWIZZLE_W;
6657 struct svga_shader_emitter_v10 *emit;
6673 emit = alloc_emitter();
6674 if (!emit)
6677 emit->unit = unit;
6678 emit->key = *key;
6680 emit->vposition.need_prescale = (emit->key.vs.need_prescale ||
6681 emit->key.gs.need_prescale);
6682 emit->vposition.tmp_index = INVALID_INDEX;
6683 emit->vposition.so_index = INVALID_INDEX;
6684 emit->vposition.out_index = INVALID_INDEX;
6686 emit->fs.color_tmp_index = INVALID_INDEX;
6687 emit->fs.face_input_index = INVALID_INDEX;
6688 emit->fs.fragcoord_input_index = INVALID_INDEX;
6690 emit->gs.prim_id_index = INVALID_INDEX;
6692 emit->clip_dist_out_index = INVALID_INDEX;
6693 emit->clip_dist_tmp_index = INVALID_INDEX;
6694 emit->clip_dist_so_index = INVALID_INDEX;
6695 emit->clip_vertex_out_index = INVALID_INDEX;
6697 if (emit->key.fs.alpha_func == SVGA3D_CMP_INVALID) {
6698 emit->key.fs.alpha_func = SVGA3D_CMP_ALWAYS;
6707 transform_fs_pstipple(emit, tokens);
6730 tgsi_scan_shader(tokens, &emit->info);
6732 emit->info = shader->info;
6735 emit->num_outputs = emit->info.num_outputs;
6740 svga_link_shaders(&gs->base.info, &emit->info, &emit->linkage);
6743 svga_link_shaders(&vs->base.info, &emit->info, &emit->linkage);
6747 svga_link_shaders(&vs->base.info, &emit->info, &emit->linkage);
6750 determine_clipping_mode(emit);
6753 if (shader->stream_output != NULL || emit->clip_mode == CLIP_DISTANCE) {
6759 emit->vposition.so_index = emit->num_outputs++;
6761 if (emit->clip_mode == CLIP_DISTANCE) {
6762 emit->clip_dist_so_index = emit->num_outputs++;
6763 if (emit->info.num_written_clipdistance > 4)
6764 emit->num_outputs++;
6772 if (!emit_vgpu10_header(emit)) {
6773 debug_printf("svga: emit VGPU10 header failed\n");
6777 if (!emit_vgpu10_instructions(emit, tokens)) {
6778 debug_printf("svga: emit VGPU10 instructions failed\n");
6782 if (!emit_vgpu10_tail(emit)) {
6783 debug_printf("svga: emit VGPU10 tail failed\n");
6787 if (emit->register_overflow) {
6799 variant->nr_tokens = emit_get_num_tokens(emit);
6800 variant->tokens = (const unsigned *)emit->buf;
6801 emit->buf = NULL; /* buffer is no longer owed by emitter context */
6808 variant->extra_const_start = emit->num_shader_consts[0];
6819 variant->pstipple_sampler_unit = emit->fs.pstipple_sampler_unit;
6826 emit->constant_color_output && emit->num_output_writes == 1;
6831 variant->uses_flat_interp = emit->uses_flat_interp;
6838 free_emitter(emit);
