Lines Matching refs:bld
35 emit_stride(const vec4_builder &bld, const src_reg &src, unsigned size,
41 const dst_reg dst = bld.vgrf(src.type,
45 bld.MOV(writemask(offset(dst, 8, i * dst_stride / 4),
61 emit_insert(const vec4_builder &bld, const src_reg &src,
70 const dst_reg tmp = bld.vgrf(src.type);
72 bld.MOV(writemask(tmp, mask), src);
74 bld.MOV(writemask(tmp, ~mask), brw_imm_d(0));
76 return emit_stride(bld, src_reg(tmp), n, has_simd4x2 ? 1 : 4, 1);
87 emit_extract(const vec4_builder &bld, const src_reg src,
94 return emit_stride(bld, src, n, 1, has_simd4x2 ? 1 : 4);
110 emit_send(const vec4_builder &bld, enum opcode op,
123 const dst_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, sz);
127 bld.exec_all().MOV(offset(payload, 8, n++),
131 bld.MOV(offset(payload, 8, n++),
135 bld.MOV(offset(payload, 8, n++),
141 const src_reg usurface = bld.emit_uniformize(surface);
144 const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD, ret_sz);
146 bld.emit(op, dst, src_reg(payload), usurface, brw_imm_ud(arg));
162 emit_untyped_read(const vec4_builder &bld,
167 return emit_send(bld, SHADER_OPCODE_UNTYPED_SURFACE_READ, src_reg(),
168 emit_insert(bld, addr, dims, true), 1,
179 emit_untyped_write(const vec4_builder &bld, const src_reg &surface,
184 const bool has_simd4x2 = (bld.shader->devinfo->gen >= 8 ||
185 bld.shader->devinfo->is_haswell);
186 emit_send(bld, SHADER_OPCODE_UNTYPED_SURFACE_WRITE, src_reg(),
187 emit_insert(bld, addr, dims, has_simd4x2),
189 emit_insert(bld, src, size, has_simd4x2),
200 emit_untyped_atomic(const vec4_builder &bld,
206 const bool has_simd4x2 = (bld.shader->devinfo->gen >= 8 ||
207 bld.shader->devinfo->is_haswell);
213 const dst_reg srcs = bld.vgrf(BRW_REGISTER_TYPE_UD);
216 bld.MOV(writemask(srcs, WRITEMASK_X), src0);
218 bld.MOV(writemask(srcs, WRITEMASK_Y), src1);
220 return emit_send(bld, SHADER_OPCODE_UNTYPED_ATOMIC, src_reg(),
221 emit_insert(bld, addr, dims, has_simd4x2),
223 emit_insert(bld, src_reg(srcs), size, has_simd4x2),
233 emit_typed_message_header(const vec4_builder &bld)
235 const vec4_builder ubld = bld.exec_all();
236 const dst_reg dst = bld.vgrf(BRW_REGISTER_TYPE_UD);
240 if (bld.shader->devinfo->gen == 7 &&
241 !bld.shader->devinfo->is_haswell) {
259 emit_typed_read(const vec4_builder &bld, const src_reg &surface,
262 const bool has_simd4x2 = (bld.shader->devinfo->gen >= 8 ||
263 bld.shader->devinfo->is_haswell);
265 emit_send(bld, SHADER_OPCODE_TYPED_SURFACE_READ,
266 emit_typed_message_header(bld),
267 emit_insert(bld, addr, dims, has_simd4x2),
273 return emit_extract(bld, tmp, size, has_simd4x2);
282 emit_typed_write(const vec4_builder &bld, const src_reg &surface,
286 const bool has_simd4x2 = (bld.shader->devinfo->gen >= 8 ||
287 bld.shader->devinfo->is_haswell);
288 emit_send(bld, SHADER_OPCODE_TYPED_SURFACE_WRITE,
289 emit_typed_message_header(bld),
290 emit_insert(bld, addr, dims, has_simd4x2),
292 emit_insert(bld, src, size, has_simd4x2),
303 emit_typed_atomic(const vec4_builder &bld,
309 const bool has_simd4x2 = (bld.shader->devinfo->gen >= 8 ||
310 bld.shader->devinfo->is_haswell);
316 const dst_reg srcs = bld.vgrf(BRW_REGISTER_TYPE_UD);
319 bld.MOV(writemask(srcs, WRITEMASK_X), src0);
321 bld.MOV(writemask(srcs, WRITEMASK_Y), src1);
323 return emit_send(bld, SHADER_OPCODE_TYPED_ATOMIC,
324 emit_typed_message_header(bld),
325 emit_insert(bld, addr, dims, has_simd4x2),
327 emit_insert(bld, src_reg(srcs), size, has_simd4x2),
