Lines Matching refs:radeon
65 int i, mtu = rmesa->radeon.glCtx.Const.MaxTextureUnits;
67 make_empty_list(&rmesa->radeon.hw.atomlist);
68 rmesa->radeon.hw.atomlist.name = "atom-list";
70 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ctx);
71 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.set);
72 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lin);
73 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.msk);
74 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.vpt);
75 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tcl);
76 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.msc);
78 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.tex[i]);
79 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.txr[i]);
80 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.cube[i]);
82 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.zbs);
83 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.mtl);
85 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.mat[i]);
87 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.lit[i]);
89 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.ucp[i]);
90 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.stp);
91 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.eye);
92 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.grd);
93 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.fog);
94 insert_at_tail(&rmesa->radeon.hw.atomlist, &rmesa->hw.glt);
99 BATCH_LOCALS(&rmesa->radeon);
100 if (rmesa->radeon.state.scissor.enabled) {
105 OUT_BATCH((rmesa->radeon.state.scissor.rect.y1 << 16) |
106 rmesa->radeon.state.scissor.rect.x1);
108 OUT_BATCH(((rmesa->radeon.state.scissor.rect.y2) << 16) |
109 (rmesa->radeon.state.scissor.rect.x2));
127 BATCH_LOCALS(&rmesa->radeon);
131 radeonEmitState(&rmesa->radeon);
146 radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
170 BATCH_LOCALS(&rmesa->radeon);
172 uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start);
173 int dwords = (rmesa->radeon.cmdbuf.cs->section_ndw - rmesa->radeon.cmdbuf.cs->section_cdw);
178 assert( rmesa->radeon.dma.flush == radeonFlushElts );
179 rmesa->radeon.dma.flush = NULL;
195 rmesa->radeon.cmdbuf.cs->cdw += dwords;
196 rmesa->radeon.cmdbuf.cs->section_cdw += dwords;
199 radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
209 radeonFinish( &rmesa->radeon.glCtx );
221 BATCH_LOCALS(&rmesa->radeon);
228 radeonEmitState(&rmesa->radeon);
231 rmesa->tcl.elt_cmd_start = rmesa->radeon.cmdbuf.cs->cdw;
258 rmesa->tcl.elt_cmd_offset = rmesa->radeon.cmdbuf.cs->cdw;
261 retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset);
267 assert(!rmesa->radeon.dma.flush);
268 rmesa->radeon.glCtx.Driver.NeedFlush |= FLUSH_STORED_VERTICES;
269 rmesa->radeon.dma.flush = radeonFlushElts;
283 BATCH_LOCALS(&rmesa->radeon);
306 rmesa->ioctl.bo = rmesa->radeon.tcl.aos[0].bo;
308 (rmesa->radeon.tcl.aos[0].offset + offset * rmesa->radeon.tcl.aos[0].stride * 4);
309 rmesa->ioctl.vertex_max = rmesa->radeon.tcl.aos[0].count;
311 BATCH_LOCALS(&rmesa->radeon);
326 OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
327 (rmesa->radeon.tcl.aos[i].stride << 8) |
328 (rmesa->radeon.tcl.aos[i + 1].components << 16) |
329 (rmesa->radeon.tcl.aos[i + 1].stride << 24));
331 voffset = rmesa->radeon.tcl.aos[i + 0].offset +
332 offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
334 voffset = rmesa->radeon.tcl.aos[i + 1].offset +
335 offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
340 OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
341 (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
342 voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
343 offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
347 voffset = rmesa->radeon.tcl.aos[i + 0].offset +
348 offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
349 radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
350 rmesa->radeon.tcl.aos[i+0].bo,
353 voffset = rmesa->radeon.tcl.aos[i + 1].offset +
354 offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
355 radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
356 rmesa->radeon.tcl.aos[i+1].bo,
361 voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
362 offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
363 radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
364 rmesa->radeon.tcl.aos[nr-1].bo,
388 rmesa->radeon.front_buffer_dirty = GL_TRUE;
395 radeon_firevertices(&rmesa->radeon);
