Lines Matching defs:MBB
58 LiveVariables::VarInfo::findKill(const MachineBasicBlock *MBB) const {
60 if (Kills[i]->getParent() == MBB)
90 MachineBasicBlock *MBB,
92 unsigned BBNum = MBB->getNumber();
97 if (VRInfo.Kills[i]->getParent() == MBB) {
102 if (MBB == DefBlock) return; // Terminate recursion
110 WorkList.insert(WorkList.end(), MBB->pred_rbegin(), MBB->pred_rend());
115 MachineBasicBlock *MBB) {
117 MarkVirtRegAliveInBlock(VRInfo, DefBlock, MBB, WorkList);
126 void LiveVariables::HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
130 unsigned BBNum = MBB->getNumber();
136 if (!VRInfo.Kills.empty() && VRInfo.Kills.back()->getParent() == MBB) {
145 assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
164 if (MBB == MRI->getVRegDef(reg)->getParent()) return;
173 for (MachineBasicBlock::const_pred_iterator PI = MBB->pred_begin(),
174 E = MBB->pred_end(); PI != E; ++PI)
507 MachineBasicBlock *MBB = *DFI;
511 for (MachineBasicBlock::livein_iterator II = MBB->livein_begin(),
512 EE = MBB->livein_end(); II != EE; ++II) {
521 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
557 HandleVirtRegUse(MOReg, MBB, MI);
577 if (!PHIVarInfo[MBB->getNumber()].empty()) {
578 SmallVector<unsigned, 4>& VarInfoVec = PHIVarInfo[MBB->getNumber()];
584 MBB);
593 if (!MBB->empty() && MBB->back().getDesc().isReturn()
594 && !MBB->back().getDesc().isCall()) {
595 MachineInstr *Ret = &MBB->back();
685 bool LiveVariables::VarInfo::isLiveIn(const MachineBasicBlock &MBB,
688 unsigned Num = MBB.getNumber();
694 // Registers defined in MBB cannot be live in.
696 if (Def && Def->getParent() == &MBB)
699 // Reg was not defined in MBB, was it killed here?
700 return findKill(&MBB);
703 bool LiveVariables::isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) {
709 for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(),
710 E = MBB.succ_end(); SI != E; ++SI) {
