Lines Matching defs:Def
107 UseSlots.push_back((*I)->def);
109 // Get use slots form the use-def chain.
192 // When not live in, the first use should be a def.
194 assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
195 assert(LVI->start == BI.FirstInstr && "First instr should be a def");
225 // A LiveRange that starts in the middle of the block must be a def.
226 assert(LVI->start == LVI->valno->def && "Dangling LiveRange start");
362 // Keep it as a simple def without any liveness.
368 SlotIndex Def = OldVNI->def;
369 LI->addRange(LiveRange(Def, Def.getNextSlot(), OldVNI));
375 SlotIndex Def = VNI->def;
376 LI->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
393 // This was previously a single mapping. Make sure the old def is represented
395 SlotIndex Def = VNI->def;
396 Edit->get(RegIdx)->addRange(LiveRange(Def, Def.getNextSlot(), VNI));
407 SlotIndex Def;
417 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, LIS, TII, TRI, Late);
423 Def = LIS.getSlotIndexes()->insertMachineInstrInMaps(CopyMI, Late)
429 VNInfo *VNI = defValue(RegIdx, ParentVNI, Def);
467 return VNI->def;
485 return VNI->def;
501 RegAssign.insert(VNI->def, End, OpenIdx);
503 return VNI->def;
537 if (SpillMode && !SlotIndex::isSameInstr(ParentVNI->def, Idx) &&
546 return VNI->def;
565 return VNI->def;
581 RegAssign.insert(Start, VNI->def, OpenIdx);
583 return VNI->def;
614 SlotIndex Def = VNI->def;
615 MachineInstr *MI = LIS.getInstructionFromIndex(Def);
624 DEBUG(dbgs() << "Removing " << Def << '\t' << *MI);
629 // Adjust RegAssign if a register assignment is killed at VNI->def. We
632 AssignI.find(VNI->def.getPrevSlot());
633 if (!AssignI.valid() || AssignI.start() >= Def)
636 if (AssignI.stop() != Def)
641 forceRecompute(RegIdx, Edit->getParent().getVNInfoAt(Def));
655 assert(MDT.dominates(DefMBB, MBB) && "MBB must be dominated by the def.");
671 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
678 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
688 DEBUG(dbgs() << "Def in BB#" << DefMBB->getNumber() << " dominates BB#"
719 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
720 assert(ParentVNI && "Parent not live at complement def");
727 MachineBasicBlock *ValMBB = LIS.getMBBFromIndex(VNI->def);
733 if (VNI->def == ParentVNI->def) {
734 DEBUG(dbgs() << "Direct complement def at " << VNI->def << '\n');
735 Dom = DomPair(ValMBB, VNI->def);
741 DEBUG(dbgs() << "Single complement def at " << VNI->def << '\n');
747 Dom = DomPair(ValMBB, VNI->def);
749 // Two defs in the same block. Pick the earlier def.
750 if (!Dom.second.isValid() || VNI->def < Dom.second)
751 Dom.second = VNI->def;
757 // Def ValMBB dominates.
758 Dom = DomPair(ValMBB, VNI->def);
760 // None dominate. Hoist to common dominator, need new def.
764 DEBUG(dbgs() << "Multi-mapped complement " << VNI->id << '@' << VNI->def
765 << " for parent " << ParentVNI->id << '@' << ParentVNI->def
777 MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(ParentVNI->def);
783 LIS.getLastSplitPoint(Edit->getParent(), Dom.first))->def;
787 // def with the same value.
792 VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(VNI->def);
794 if (!Dom.first || Dom.second == VNI->def)
861 // The first block may be live-in, or it may have its own def.
864 assert(VNI && "Missing def for complex mapped value");
866 // MBB has its own def. Is it also live-out?
880 if (BlockStart == ParentVNI->def) {
881 // This block has the def of a parent PHI, so it isn't live-in.
884 assert(VNI && "Missing def for complex mapped parent PHI");
922 unsigned RegIdx = RegAssign.lookup(PHIVNI->def);
925 MachineBasicBlock *MBB = LIS.getMBBFromIndex(PHIVNI->def);
957 // which register we choose. When the use operand is tied to a def, we must
958 // use the same register as the def, so just do that always.
998 if (LII->end != LII->valno->def.getNextSlot())
1000 MachineInstr *MI = LIS.getInstructionFromIndex(LII->valno->def);
1001 assert(MI && "Missing instruction for dead def");
1030 unsigned RegIdx = RegAssign.lookup(ParentVNI->def);
1031 VNInfo *VNI = defValue(RegIdx, ParentVNI, ParentVNI->def);
1370 // >>>> Interference before def.
1382 // >>>> Interference before def.
