Lines Matching refs:Imm
105 // reg [asr|lsl|lsr|ror|rrx] imm
108 // reg, the second is the shift amount (or reg0 if not present or imm). The
109 // third operand encodes the shift opcode and the imm if a reg isn't present.
111 static inline unsigned getSORegOpc(ShiftOpc ShOp, unsigned Imm) {
112 return ShOp | (Imm << 3);
121 /// getSOImmValImm - Given an encoded imm field for the reg/imm form, return
122 /// the 8-bit imm value.
123 static inline unsigned getSOImmValImm(unsigned Imm) {
124 return Imm & 0xFF;
126 /// getSOImmValRot - Given an encoded imm field for the reg/imm form, return
128 static inline unsigned getSOImmValRot(unsigned Imm) {
129 return (Imm >> 8) * 2;
132 /// getSOImmValRotate - Try to handle Imm with an immediate shifter operand,
136 static inline unsigned getSOImmValRotate(unsigned Imm) {
139 if ((Imm & ~255U) == 0) return 0;
142 unsigned TZ = CountTrailingZeros_32(Imm);
149 if ((rotr32(Imm, RotAmt) & ~255U) == 0)
154 if (Imm & 63U) {
155 unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U);
157 if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
215 /// getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed
217 static inline unsigned getThumbImmValShift(unsigned Imm) {
220 if ((Imm & ~255U) == 0) return 0;
223 return CountTrailingZeros_32(Imm);
234 /// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
236 static inline unsigned getThumbImm16ValShift(unsigned Imm) {
239 if ((Imm & ~65535U) == 0) return 0;
242 return CountTrailingZeros_32(Imm);
270 unsigned u, Vs, Imm;
278 Imm = Vs & 0xff;
280 u = Imm | (Imm << 16);
284 return (((Vs == V) ? 1 : 2) << 8) | Imm;
288 return (3 << 8) | Imm;
334 static inline bool isT2SOImmTwoPartVal (unsigned Imm) {
335 unsigned V = Imm;
349 V = Imm;
361 static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) {
362 assert (isT2SOImmTwoPartVal(Imm) &&
365 unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm;
370 if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
371 return Imm & 0xff00ff00U;
374 assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
375 return Imm & 0x00ff00ffU;
378 static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) {
380 Imm ^= getT2SOImmTwoPartFirst(Imm);
382 assert (getT2SOImmVal(Imm) != -1 &&
384 return Imm;
394 // addrmode2 := reg +/- reg shop imm
408 assert(Imm12 < (1 << 12) && "Imm too large!");
582 static inline float getFPImmFloat(unsigned Imm) {
589 uint8_t Sign = (Imm >> 7) & 0x1;
590 uint8_t Exp = (Imm >> 4) & 0x7;
591 uint8_t Mantissa = Imm & 0xf;
610 static inline int getFP32Imm(const APInt &Imm) {
611 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
612 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
613 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
638 static inline int getFP64Imm(const APInt &Imm) {
639 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
640 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
641 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL;
