Lines Matching refs:BF
39 : BlackfinGenRegisterInfo(BF::RETS), Subtarget(st), TII(tii) {}
43 using namespace BF;
56 using namespace BF;
97 BuildMI(MBB, I, DL, TII.get(BF::ADDpp_imm7), Reg)
105 if (BF::PRegClass.contains(Reg)) {
106 assert(BF::PRegClass.contains(ScratchReg) &&
108 BuildMI(MBB, I, DL, TII.get(BF::ADDpp), Reg)
112 assert(BF::DRegClass.contains(Reg) && "Reg must be a D or P register");
113 assert(BF::DRegClass.contains(ScratchReg) &&
115 BuildMI(MBB, I, DL, TII.get(BF::ADD), Reg)
128 BuildMI(MBB, I, DL, TII.get(BF::LOADimm7), Reg).addImm(value);
133 BuildMI(MBB, I, DL, TII.get(BF::LOADuimm16), Reg).addImm(value);
138 BuildMI(MBB, I, DL, TII.get(BF::LOADimm16), Reg).addImm(value);
144 TII.get(BF::LOAD16i), getSubReg(Reg, BF::hi16))
148 TII.get(BF::LOAD16i), getSubReg(Reg, BF::lo16))
164 if (I->getOpcode() == BF::ADJCALLSTACKDOWN) {
165 adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, -Amount);
167 assert(I->getOpcode() == BF::ADJCALLSTACKUP &&
169 adjustRegister(MBB, I, I->getDebugLoc(), BF::SP, BF::P1, Amount);
207 unsigned BaseReg = BF::FP;
211 BaseReg = BF::SP;
218 case BF::STORE32fi:
220 case BF::LOAD32fi: {
227 ? BF::STORE32p_uimm6m4
228 : BF::LOAD32p_uimm6m4));
231 if (BaseReg == BF::FP && isUInt<7>(-Offset)) {
233 ? BF::STORE32fp_nimm7m4
234 : BF::LOAD32fp_nimm7m4));
240 ? BF::STORE32p_imm18m4
241 : BF::LOAD32p_imm18m4));
249 case BF::ADDpp: {
261 case BF::STORE16fi:
263 case BF::LOAD16fi: {
267 unsigned ScratchReg = findScratchRegister(II, RS, &BF::PRegClass, SPAdj);
270 BuildMI(MBB, II, DL, TII.get(BF::ADDpp), ScratchReg)
273 MI.setDesc(TII.get(isStore ? BF::STORE16pi : BF::LOAD16pi));
278 case BF::STORE8fi: {
282 unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
284 if (SpillReg.getReg()==BF::NCC) {
285 BuildMI(MBB, II, DL, TII.get(BF::MOVENCC_z), ScratchReg)
287 BuildMI(MBB, II, DL, TII.get(BF::BITTGL), ScratchReg)
290 BuildMI(MBB, II, DL, TII.get(BF::MOVECC_zext), ScratchReg)
294 MI.setDesc(TII.get(BF::STORE8p_imm16));
300 case BF::LOAD8fi: {
304 unsigned ScratchReg = findScratchRegister(II, RS, &BF::DRegClass, SPAdj);
306 MI.setDesc(TII.get(BF::LOAD32p_imm16_8z));
311 if (SpillReg.getReg()==BF::CC) {
313 BuildMI(MBB, II, DL, TII.get(BF::MOVECC_nz), BF::CC)
317 BuildMI(MBB, II, DL, TII.get(BF::SETEQri_not), BF::NCC)
333 return TFI->hasFP(MF) ? BF::FP : BF::SP;
