Lines Matching defs:B24
60 static constexpr IValueT B24 = 1 << 24;
1068 B25 | B24 | B20 | B15 | B14 | B13 | B12 | B4 |
1258 B24 | B23 | B21 | B20 | B19 | B17 | B16 | B10 | B9 | Opcode;
1389 const IValueT Encoding = (CondARM32::AL << kConditionShift) | B24 | B21 |
1437 int32_t Encoding = (encodeCondition(Cond) << kConditionShift) | B24 | B21 |
1448 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B24 |
1471 B24 | B22 | B21 | (0xF << 16) | (0xf << 8) | B4;
1520 (encodeCondition(CondARM32::kNone) << kConditionShift) | B26 | B24 | B22 |
1650 IValueT Encoding = (Cond << kConditionShift) | B24 | B23 | B11 | B10 | B9 |
1775 IValueT Opcode = B25 | B24 | (IsMovW ? 0 : B22);
1848 B24 | B21 | B15 | B14 | B13 | B12;
2364 B24 | B23 | B21 | B20 | B16 | B9 | B8 | (encodeElmtType(ElmtTy) << 18);
2439 constexpr IValueT VbslqOpcode = B24 | B20 | B8 | B4;
2452 constexpr IValueT VceqOpcode = B24 | B11 | B4;
2488 constexpr IValueT VcgeOpcode = B24 | B9 | B8 | B4;
2499 constexpr IValueT VcgeOpcode = B24
2524 constexpr IValueT VcgeOpcode = B24 | B9 | B8;
2535 constexpr IValueT VcgeOpcode = B24 | B21 | B11 | B10 | B9;
2819 B25 | B24 | B8 | B4 |
2834 constexpr IValueT VeorqOpcode = B24 | B8 | B4;
2853 IValueT Encoding = B27 | B26 | B24 | B20 | B11 | B9 | B8 |
2878 IValueT Encoding = B27 | B26 | B24 | B20 | B11 | B9 | B8 |
2900 IValueT Encoding = B27 | B26 | B24 | B20 | B11 | B9 |
3355 B25 | (Unsigned ? B24 : 0) | B23 | (B20) | B11 | B10;
3399 B25 | (Unsigned ? B24 : 0) | B23 | (B20) | B11 | B10;
3430 const IValueT VdupOpcode = B25 | B24 | B23 | B21 | B20 | B11 | B10;
3501 constexpr IValueT VzipOpcode = B25 | B24 | B23 | B21 | B20 | B17 | B8 | B7;
3506 constexpr IValueT VtrnOpcode = B25 | B24 | B23 | B21 | B20 | B17 | B7;
3520 constexpr IValueT VmulqfOpcode = B24 | B11 | B8 | B4;
3532 constexpr IValueT VmvnOpcode = B24 | B23 | B21 | B20 | B10 | B8 | B7;
3657 constexpr IValueT VnegOpcode = B24 | B23 | B21 | B20 | B16 | B9 | B8 | B7;
3697 IValueT Encoding = B27 | B26 | B24 | B11 | B9 | B8 |
3722 IValueT Encoding = B27 | B26 | B24 | B11 | B9 | B8 |
3745 B27 | B26 | B24 | B11 | B9 | (encodeCondition(Cond) << kConditionShift) |
3851 constexpr IValueT VqaddquOpcode = B24 | B4;
3879 constexpr IValueT VqsubquOpcode = B24 | B9 | B4;
3893 constexpr IValueT VsubqiOpcode = B24 | B11;
3922 IValueT VqmovnOpcode = B25 | B24 | B23 | B21 | B20 | B17 | B9 |
4004 B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
4050 (Sign == InstARM32::FS_Unsigned ? B24 : 0) | B23 | B4;
4065 constexpr IValueT VshlOpcode = B24 | B10 | B6;
