Lines Matching refs:Dm
1201 IValueT Dm, bool UseQRegs, bool IsFloatTy) {
1207 (getYInRegYXXXX(Dm) << 5) | getXXXXInRegYXXXX(Dm);
1212 IValueT Dn, IValueT Dm, bool UseQRegs) {
1216 emitSIMDBase(Opcode | (ElmtSize << ElmtShift), Dd, Dn, Dm, UseQRegs,
1269 IValueT Dd, IValueT Dn, IValueT Dm) {
1272 assert(Dm < RegARM32::getNumDRegs());
1279 (getYInRegYXXXX(Dm) << 5) | getXXXXInRegYXXXX(Dm);
1288 IValueT Dm = encodeDRegister(OpDm, "Dm", InstName);
1289 emitVFPddd(Cond, Opcode, Dd, Dn, Dm);
2340 // vabs<c>.f64 <Dd>, <Dm>
2342 // cccc11101D110000dddd101111M0mmmm where cccc=Cond, Ddddd=Dd, and Mmmmm=Dm.
2345 const IValueT Dm = encodeDRegister(OpDm, "Dm", Vabsd);
2348 emitVFPddd(Cond, VabsdOpcode, Dd, D0, Dm);
2361 const IValueT Dm = mapQRegToDReg(encodeQRegister(OpQm, "Qm", Vabsq));
2366 emitSIMDBase(VabsqOpcode, Dd, Dn, Dm, UseQRegs, isFloatingType(ElmtTy));
2411 // vadd<c>.f64 <Dd>, <Dn>, <Dm>
2544 IValueT Dm = encodeDRegister(OpDm, "Dm", Vcmpd);
2547 emitVFPddd(Cond, VcmpdOpcode, Dd, Dn, Dm);
2555 constexpr IValueT Dm = 0;
2556 emitVFPddd(Cond, VcmpdzOpcode, Dd, Dn, Dm);
2579 IValueT Dm) {
2581 assert(Dm < RegARM32::getNumDRegs());
2587 (getYInRegYXXXX(Dm) << 5) | getXXXXInRegYXXXX(Dm);
2623 IValueT Dm = encodeDRegister(OpDm, "Dm", Vcvtsd);
2626 emitVFPsd(Cond, VcvtsdOpcode, Sd, Dm);
2648 // vcvt<c>.s32.f64 <Sd>, <Dm>
2650 // cccc11101D111101dddd10111M0mmmm where cccc=Cond, ddddD=Sd, and Mmmmm=Dm.
2653 IValueT Dm = encodeDRegister(OpDm, "Dm", Vcvtid);
2656 emitVFPsd(Cond, VcvtidOpcode, Sd, Dm);
2693 // vcvt<c>.u32.f64 <Sd>, <Dm>
2695 // cccc11101D111100dddd10111M0mmmm where cccc=Cond, ddddD=Sd, and Mmmmm=Dm.
2698 IValueT Dm = encodeDRegister(OpDm, "Dm", Vcvtud);
2700 emitVFPsd(Cond, VcvtudOpcode, Sd, Dm);
2799 // vdiv<c>.f64 <Dd>, <Dn>, <Dm>
2811 // veor<c> <Dd>, <Dn>, <Dm>
2813 // 111100110D00nnnndddd0001N0M1mmmm where Ddddd=Dd, Nnnnn=Dn, and Mmmmm=Dm.
2817 IValueT Dm = encodeDRegister(OpDm, "Dm", Veord);
2823 (getYInRegYXXXX(Dm) << 5) | getXXXXInRegYXXXX(Dm);
3079 IValueT Dm = encodeSRegister(OpDm, "Dm", Vmovdd);
3082 emitVFPddd(Cond, VmovddOpcode, Dd, D0, Dm);
3089 // vmov<c> <Dm>, <Rt>, <Rt2>
3092 // Mmmmm=Dm.
3094 IValueT Dm = encodeDRegister(OpDm, "Dm", Vmovdrr);
3105 (Rt << 12) | (getYInRegYXXXX(Dm) << 5) |
3106 getXXXXInRegYXXXX(Dm);
3141 // vmov<c> <Rt>, <Rt2>, <Dm>
3144 // Mmmmm=Dm.
3148 IValueT Dm = encodeDRegister(OpDm, "Dm", Vmovrrd);
3157 (Rt << 12) | (getYInRegYXXXX(Dm) << 5) |
3158 getXXXXInRegYXXXX(Dm);
3238 // vmla<c>.f64 <Dd>, <Dn>, <Dm>
3241 // Mmmmm=Dm
3262 // vmls<c>.f64 <Dd>, <Dn>, <Dm>
3265 // Mmmmm=Dm
3311 // vmul<c>.f64 <Dd>, <Dn>, <Dm>
3342 // VMUL<c>.<dt> <Dd>, <Dn>, <Dm>
3363 const IValueT Dm = mapQRegToDReg(Qm);
3367 emitSIMDBase(VmullOpcode | (ElmtSize << ElmtShift), Dd, Dn, Dm, UseQRegs,
3403 const IValueT Dm = mapQRegToDReg(encodeQRegister(OpQm, "Qm", Vmull));
3407 emitSIMDBase(VmullOpcode | (ElmtSize << ElmtShift), Dd, Dn, Dm, UseQRegs,
3411 // vpadd.<dt> <Dd>, <Dm>, <Dn>
3413 // 111100100Dssnnnndddd1011NQM1mmmm where Ddddd=<Dd>, Mmmmm=<Dm>, and
3424 // VDUP<c>.<size> <Qd>, <Dm[x]>
3426 // 111100111D11iiiiddd011000QM0mmmm where Dddd=<Qd>, Mmmmm=<Dm>, and
3471 // VZIP<c>.<size> <Dd>, <Dm>
3473 // 111100111D11ss10dddd00011QM0mmmm where Ddddd=<Dd>, Mmmmm=<Dm>, and
3480 const IValueT Dm = mapQRegToDReg(encodeQRegister(OpQm, "Qm", Vzip));
3485 // VMOV Dd, Dm
3490 emitSIMDBase(VmovOpcode, Dd + 1, Dm, Dm, UseQRegs, IsFloatTy);
3548 // VMOV<c> <Dd>, <Dm>
3555 const IValueT Dm = mapQRegToDReg(encodeQRegister(OpQm, "Qm", Vmov));
3562 if (Dd != Dm)
3563 emitSIMDBase(VmovOpcode, Dd, Dm, Dm, UseQRegs, IsFloat);
3574 // VMOV<c> <Dd>, <Dm>
3581 const IValueT Dm = mapQRegToDReg(encodeQRegister(OpQm, "Qm", Vmov));
3590 if (Dd + 1 != Dm + 1)
3591 emitSIMDBase(VmovOpcode, Dd + 1, Dm + 1, Dm + 1, UseQRegs, IsFloat);
3600 // VMOV<c> <Dd>, <Dm>
3607 const IValueT Dm = mapQRegToDReg(encodeQRegister(OpQm, "Qm", Vmov));
3614 if (Dd != Dm + 1)
3615 emitSIMDBase(VmovOpcode, Dd, Dm + 1, Dm + 1, UseQRegs, IsFloat);
3626 // VMOV<c> <Dd>, <Dm>
3633 const IValueT Dm = mapQRegToDReg(encodeQRegister(OpQm, "Qm", Vmov));
3640 if (Dd + 1 != Dm)
3641 emitSIMDBase(VmovOpcode, Dd + 1, Dm, Dm, UseQRegs, IsFloat);
3818 // vsub<c>.f64 <Dd>, <Dn>, <Dm>
3919 const IValueT Dm = mapQRegToDReg(Qm);
3932 emitSIMDBase(VqmovnOpcode, Dd + 0, 0, Dm, UseQRegs, IsFloatTy);
3935 emitSIMDBase(VqmovnOpcode, Dd + 0, 0, Dm, UseQRegs, IsFloatTy);
3940 emitSIMDBase(VqmovnOpcode, Dd, 0, Dm, UseQRegs, IsFloatTy);
3942 // VMOV Dd, Dm
4072 // vsqrt<c>.f64 <Dd>, <Dm>
4077 IValueT Dm = encodeDRegister(OpDm, "Dm", Vsqrtd);
4080 emitVFPddd(Cond, VsqrtdOpcode, Dd, D0, Dm);
