Lines Matching refs:Encoding
65 // Constants used for the decoding or encoding of the individual fields of
87 // Immediate instruction fields encoding.
111 // Type of instruction encoding (bits 25-27). See ARM section A5.1
148 // Follows encoding in ARM section A8.4.1 "Constant shifts".
250 // Alternate encoding for RotatedImm8Address, where the offset is divided by 4
251 // before encoding.
257 // Alternate encoding 3, for an address modified by a rotated immediate 8-bit
261 // Encoding where no immediate offset is used.
325 // Sets Encoding to a rotated Imm8 encoding of Value, if possible.
435 // Encodes immediate register offset using encoding 3.
807 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) |
811 emitInst(Encoding);
877 // nnnn=Rn, ssss=Rs, f=SetFlags, tt is encoding of type, and
892 IValueT Encoding = static_cast<int32_t>(Cond) << kConditionShift |
894 Encoding = encodeBranchOffset(Offset, Encoding);
895 emitInst(Encoding);
938 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) |
941 emitInst(Encoding);
1025 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) |
1027 emitInst(Encoding);
1049 // For encoding 3, no shift is allowed.
1052 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) |
1054 emitInst(Encoding);
1066 const IValueT Encoding = Opcode | (encodeCondition(Cond) << kConditionShift) |
1070 emitInst(Encoding);
1108 const IValueT Encoding = B27 | B26 | B25 | B11 | B9 | B8 | B4 |
1114 emitInst(Encoding);
1118 // VMOV (register) - ARM section A8.8.340, encoding A2:
1135 IValueT Encoding = Opcode | (encodeCondition(Cond) << kConditionShift) |
1139 emitInst(Encoding);
1148 IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 |
1151 emitInst(Encoding);
1170 // SXTB/UXTB - Arm sections A8.8.233 and A8.8.274, encoding A1:
1179 // SXTH/UXTH - ARM sections A8.8.235 and A8.8.276, encoding A1:
1194 IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | Opcode |
1197 emitInst(Encoding);
1202 const IValueT Encoding =
1208 emitInst(Encoding);
1275 const IValueT Encoding =
1280 emitInst(Encoding);
1299 const IValueT Encoding =
1304 emitInst(Encoding);
1319 // ADC (register) - ARM section 18.8.2, encoding A1:
1325 // ADC (Immediate) - ARM section A8.8.1, encoding A1:
1339 // ADD (register) - ARM section A8.8.7, encoding A1:
1341 // ADD (Sp plus register) - ARM section A8.8.11, encoding A1:
1347 // ADD (Immediate) - ARM section A8.8.5, encoding A1:
1349 // ADD (SP plus immediate) - ARM section A8.8.9, encoding A1.
1363 // AND (register) - ARM section A8.8.14, encoding A1:
1369 // AND (Immediate) - ARM section A8.8.13, encoding A1:
1385 // BKPT - ARM section A*.8.24 - encoding A1:
1389 const IValueT Encoding = (CondARM32::AL << kConditionShift) | B24 | B21 |
1391 emitInst(Encoding);
1397 // BIC (register) - ARM section A8.8.22, encoding A1:
1403 // BIC (immediate) - ARM section A8.8.21, encoding A1:
1415 // BL (immediate) - ARM section A8.8.25, encoding A1:
1428 // BLX (register) - ARM section A8.8.26, encoding A1:
1437 int32_t Encoding = (encodeCondition(Cond) << kConditionShift) | B24 | B21 |
1439 emitInst(Encoding);
1443 // BX - ARM section A8.8.27, encoding A1:
1448 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B24 |
1451 emitInst(Encoding);
1456 // CLZ - ARM section A8.8.33, encoding A1:
1472 const IValueT Encoding = PredefinedBits | (Cond << kConditionShift) |
1474 emitInst(Encoding);
1479 // CMN (immediate) - ARM section A8.8.34, encoding A1:
1497 // CMP (register) - ARM section A8.8.38, encoding A1:
1514 // DMB - ARM section A8.8.43, encoding A1:
1519 const IValueT Encoding =
1523 emitInst(Encoding);
1529 // EOR (register) - ARM section A*.8.47, encoding A1:
1535 // EOR (Immediate) - ARM section A8.*.46, encoding A1:
1564 // LDRB (immediate) - ARM section A8.8.68, encoding A1:
1573 // LDRB (register) - ARM section A8.8.66, encoding A1:
1584 // LDRH (immediate) - ARM section A8.8.80, encoding A1:
1597 // LDR (immediate) - ARM section A8.8.63, encoding A1:
1605 // LDR (register) - ARM section A8.8.70, encoding A1:
1650 IValueT Encoding = (Cond << kConditionShift) | B24 | B23 | B11 | B10 | B9 |
1653 emitInst(Encoding);
1659 // LDREXB - ARM section A8.8.76, encoding A1:
1664 // LDREXH - ARM section A8.8.78, encoding A1:
1669 // LDREX - ARM section A8.8.75, encoding A1:
1751 // MOV (register) - ARM section A8.8.104, encoding A1:
1757 // MOV (immediate) - ARM section A8.8.102, encoding A1:
1789 const IValueT Encoding = encodeCondition(Cond) << kConditionShift | Opcode |
1792 emitInst(Encoding);
1797 // MOV (immediate) - ARM section A8.8.102, encoding A2:
1809 // MOVT - ARM section A8.8.106, encoding A1:
1821 // MVN (immediate) - ARM section A8.8.115, encoding A1:
1827 // MVN (register) - ARM section A8.8.116, encoding A1:
1842 // NOP - Section A8.8.119, encoding A1:
1847 const IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B25 |
1849 emitInst(Encoding);
1855 // SBC (register) - ARM section 18.8.162, encoding A1:
1861 // SBC (Immediate) - ARM section A8.8.161, encoding A1:
1874 // SDIV - ARM section A8.8.165, encoding A1.
1909 // STRB (immediate) - ARM section A8.8.207, encoding A1:
1921 // STRH (immediate) - ARM section A8.*.217, encoding A1:
1937 // STR (immediate) - ARM section A8.8.207, encoding A1:
1954 // STREXB - ARM section A8.8.213, encoding A1:
1960 // STREXH - ARM section A8.8.215, encoding A1:
1966 // STREX - ARM section A8.8.212, encoding A1:
1972 // STREXD - ARM section A8.8.214, encoding A1:
1978 // Note: Rt uses Rm shift in encoding.
1988 // ORR (register) - ARM Section A8.8.123, encoding A1:
1994 // ORR (register) - ARM Section A8.8.123, encoding A1:
2006 // POP - ARM section A8.8.132, encoding A2:
2025 // POP - ARM section A8.*.131, encoding A1:
2035 // PUSH - ARM section A8.8.133, encoding A2:
2054 // PUSH - ARM section A8.8.133, encoding A1:
2066 // MLA - ARM section A8.8.114, encoding A1.
2107 // MUL - ARM section A8.8.114, encoding A1.
2129 IValueT Encoding =
2131 emitInst(Encoding);
2136 // RBIT - ARM section A8.8.144, encoding A1:
2148 // REV - ARM section A8.8.145, encoding A1:
2161 // RSB (immediate) - ARM section A8.8.152, encoding A1.
2167 // RSB (register) - ARM section A8.8.163, encoding A1.
2181 // RSC (immediate) - ARM section A8.8.155, encoding A1:
2187 // RSC (register) - ARM section A8.8.156, encoding A1:
2193 // RSC (register-shifted register) - ARM section A8.8.157, encoding A1:
2214 // SUB (register) - ARM section A8.8.223, encoding A1:
2216 // SUB (SP minus register): See ARM section 8.8.226, encoding A1:
2222 // Sub (Immediate) - ARM section A8.8.222, encoding A1:
2224 // Sub (Sp minus immediate) - ARM section A8.8.225, encoding A1:
2237 // Use a particular UDF encoding -- TRAPNaCl in LLVM: 0xE7FEDEF0
2258 // TST (register) - ARM section A8.8.241, encoding A1:
2264 // TST (immediate) - ARM section A8.8.240, encoding A1:
2276 // UDIV - ARM section A8.8.248, encoding A1.
2296 // UMULL - ARM section A8.8.257, encoding A1:
2325 // VABS - ARM section A8.8.280, encoding A2:
2339 // VABS - ARM section A8.8.280, encoding A2:
2352 // VABS - ARM section A8.8.280, encoding A1:
2356 // <dt> in {s8, s16, s32, f32} and ss is the encoding of <dt>.
2371 // VADD (floating-point) - ARM section A8.8.283, encoding A2:
2383 // VADD (integer) - ARM section A8.8.282, encoding A1:
2397 // VADD (floating-point) - ARM section A8.8.283, Encoding A1:
2410 // VADD (floating-point) - ARM section A8.8.283, encoding A2:
2422 // VAND (register) - ARM section A8.8.287, encoding A1:
2434 // VBSL (register) - ARM section A8.8.290, encoding A1:
2446 // vceq (register) - ARM section A8.8.291, encoding A1:
2458 // vceq (register) - ARM section A8.8.291, encoding A2:
2470 // vcge (register) - ARM section A8.8.293, encoding A1:
2482 // vcge (register) - ARM section A8.8.293, encoding A1:
2494 // vcge (register) - ARM section A8.8.293, encoding A2:
2506 // vcgt (register) - ARM section A8.8.295, encoding A1:
2518 // vcgt (register) - ARM section A8.8.295, encoding A1:
2530 // vcgt (register) - ARM section A8.8.295, encoding A2:
2584 const IValueT Encoding =
2588 emitInst(Encoding);
2594 // - ARM Section A8.8.306, encoding A1:
2608 // - ARM Section A8.8.306, encoding A1:
2632 // - ARM Section A8.8.306, encoding A1:
2647 // - ARM Section A8.8.306, encoding A1:
2662 // - ARM Section A8.8.306, encoding A1:
2677 // - ARM Section A8.8.306, encoding A1:
2692 // - ARM Section A8.8.306, encoding A1:
2706 // - ARM Section A8.8.306, encoding A1:
2720 // - ARM Section A8.8.305, encoding A1:
2731 // - ARM Section A8.8.305, encoding A1:
2742 // - ARM Section A8.8.305, encoding A1:
2753 // - ARM Section A8.8.305, encoding A1:
2768 const IValueT Encoding =
2772 emitInst(Encoding);
2786 // VDIV (floating-point) - ARM section A8.8.283, encoding A2:
2798 // VDIV (floating-point) - ARM section A8.8.283, encoding A2:
2810 // VEOR - ARM secdtion A8.8.315, encoding A1:
2818 const IValueT Encoding =
2824 emitInst(Encoding);
2829 // VEOR - ARM section A8.8.316, encoding A1:
2840 // VLDR - ARM section A8.8.333, encoding A1.
2853 IValueT Encoding = B27 | B26 | B24 | B20 | B11 | B9 | B8 |
2857 emitInst(Encoding);
2865 // VLDR - ARM section A8.8.333, encoding A1.
2878 IValueT Encoding = B27 | B26 | B24 | B20 | B11 | B9 | B8 |
2882 emitInst(Encoding);
2887 encoding A2.
2900 IValueT Encoding = B27 | B26 | B24 | B20 | B11 | B9 |
2904 emitInst(Encoding);
2932 const IValueT Encoding =
2937 emitInst(Encoding);
2964 const IValueT Encoding =
2969 emitInst(Encoding);
2974 // VLD1 (multiple single elements) - ARM section A8.8.320, encoding A1:
2979 // encoding of ElmtSize.
3003 // VLD1 (single elements to one lane) - ARMv7-A/R section A8.6.308, encoding
3009 // encoding of ElmtSize.
3025 // VMOV (immediate) - ARM section A8.8.320, encoding A1:
3045 const IValueT Encoding =
3050 emitInst(Encoding);
3057 // VMOV (immediate) - ARM section A8.8.339, encoding A2:
3073 // VMOV (register) - ARM section A8.8.340, encoding A2:
3088 // ARM section A8.8.345, encoding A1:
3103 IValueT Encoding = B27 | B26 | B22 | B11 | B9 | B8 | B4 |
3107 emitInst(Encoding);
3112 // VMOV (ARM core register to scalar) - ARM section A8.8.341, encoding A1:
3130 // VMOV (scalar to ARM core register) - ARM section A8.8.342, encoding A1:
3140 // ARM section A8.8.345, encoding A1:
3155 IValueT Encoding = B27 | B26 | B22 | B20 | B11 | B9 | B8 | B4 |
3159 emitInst(Encoding);
3165 // ARM section A8.8.343, encoding A1.
3174 IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 | B26 |
3177 emitInst(Encoding);
3183 // VMOV (immediate) - ARM section A8.8.339, encoding A2:
3218 // ARM section A8.8.343, encoding A1.
3229 IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 | B26 |
3232 emitInst(Encoding);
3237 // VMLA, VMLS (floating-point), ARM section A8.8.337, encoding A2:
3249 // VMLA, VMLS (floating-point), ARM section A8.8.337, encoding A2:
3261 // VMLA, VMLS (floating-point), ARM section A8.8.337, encoding A2:
3273 // VMLA, VMLS (floating-point), ARM section A8.8.337, encoding A2:
3284 // MVRS - ARM section A*.8.348, encoding A1:
3290 IValueT Encoding = B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 | B15 | B14 |
3293 emitInst(Encoding);
3298 // VMUL (floating-point) - ARM section A8.8.351, encoding A2:
3310 // VMUL (floating-point) - ARM section A8.8.351, encoding A2:
3322 // VMUL, VMULL (integer and polynomial) - ARM section A8.8.350, encoding A1:
3341 // VMULL (integer and polynomial) - ARMv7-A/R section A8.6.337, encoding A1:
3384 // VMULL (integer and polynomial) - ARM section A8.8.350, encoding A1:
3410 // VPADD - ARM section A8.8.280, encoding A1:
3414 // Nnnnn=<Dn> and ss is the encoding of <dt>.
3423 // VDUP (scalar) - ARMv7-A/R section A8.6.302, encoding A1:
3470 // Vzip - ARMv7-A/R section A8.6.410, encoding A1:
3514 // VMUL (floating-point) - ARM section A8.8.351, encoding A1:
3526 // VMVN (integer) - ARM section A8.8.354, encoding A1:
3547 // VMOV (register) - ARMv7-A/R section A8.6.327, encoding A1:
3573 // VMOV (register) - ARMv7-A/R section A8.6.327, encoding A1:
3599 // VMOV (register) - ARMv7-A/R section A8.6.327, encoding A1:
3625 // VMOV (register) - ARMv7-A/R section A8.6.327, encoding A1:
3648 // VNEG - ARM section A8.8.355, encoding A1:
3672 // VORR (register) - ARM section A8.8.360, encoding A1:
3684 // VSTR - ARM section A8.8.413, encoding A1:
3697 IValueT Encoding = B27 | B26 | B24 | B11 | B9 | B8 |
3701 emitInst(Encoding);
3709 // VSTR - ARM section A8.8.413, encoding A1:
3722 IValueT Encoding = B27 | B26 | B24 | B11 | B9 | B8 |
3726 emitInst(Encoding);
3731 // VSTR - ARM section A8.8.413, encoding A2:
3744 IValueT Encoding =
3747 emitInst(Encoding);
3752 // VST1 (multiple single elements) - ARM section A8.8.404, encoding A1:
3757 // encoding of ElmtSize.
3782 // VST1 (single element from one lane) - ARMv7-A/R section A8.6.392, encoding
3788 // encoding of ElmtSize.
3805 // VSUB (floating-point) - ARM section A8.8.415, encoding A2:
3817 // VSUB (floating-point) - ARM section A8.8.415, encoding A2:
3829 // VQADD (integer) - ARM section A8.6.369, encoding A1:
3843 // VQADD (integer) - ARM section A8.6.369, encoding A1:
3857 // VQSUB (integer) - ARM section A8.6.369, encoding A1:
3871 // VQSUB (integer) - ARM section A8.6.369, encoding A1:
3885 // VSUB (integer) - ARM section A8.8.414, encoding A1:
3903 // VQMOVN - ARMv7-A/R section A8.6.361, encoding A1:
3952 // VSUB (floating-point) - ARM section A8.8.415, Encoding A1:
3973 const IValueT Encoding = Opcode | (Cond << kConditionShift) | DLastBit |
3975 emitInst(Encoding);
3983 // VPOP - ARM section A8.8.367, encoding A2:
3998 // VPUSH - ARM section A8.8.368, encoding A2:
4010 // VSHL - ARM section A8.8.396, encoding A1:
4025 // VSHL - ARM section A8.8.395, encoding A1:
4041 // VSHR - ARM section A8.8.398, encoding A1:
4057 // VSHL - ARM section A8.8.396, encoding A1:
4071 // VSQRT - ARM section A8.8.401, encoding A1:
4085 // VSQRT - ARM section A8.8.401, encoding A1:
