Lines Matching refs:Qn
1078 IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", InstName));
1224 const IValueT Qn = encodeQRegister(OpQn, "Qn", OpcodeName);
1227 emitSIMDBase(Opcode, mapQRegToDReg(Qd), mapQRegToDReg(Qn), mapQRegToDReg(Qm),
1245 const IValueT Qn = 0;
1251 mapQRegToDReg(Qn), mapQRegToDReg(Qm), UseQRegs, IsFloatTy);
1262 constexpr IValueT Qn = 0;
1264 emitSIMDBase(SIMDOpcode, mapQRegToDReg(Qd), mapQRegToDReg(Qn),
2384 // vadd.<dt> <Qd>, <Qn>, <Qm>
2398 // vadd.f32 <Qd>, <Qn>, <Qm>
2400 // 111100100D00nnn0ddd01101N1M0mmm0 where Dddd=Qd, Nnnn=Qn, and Mmmm=Qm.
2423 // vand <Qd>, <Qn>, <Qm>
2435 // vbsl <Qd>, <Qn>, <Qm>
2447 // vceq.<st> <Qd>, <Qn>, <Qm>
2459 // vceq.f32 <Qd>, <Qn>, <Qm>
2471 // vcge.<st> <Qd>, <Qn>, <Qm>
2483 // vcge.<st> <Qd>, <Qn>, <Qm>
2495 // vcge.f32 <Qd>, <Qn>, <Qm>
2507 // vcgt.<st> <Qd>, <Qn>, <Qm>
2519 // vcgt.<st> <Qd>, <Qn>, <Qm>
2531 // vcgt.f32 <Qd>, <Qn>, <Qm>
2830 // veor <Qd>, <Qn>, <Qm>
2832 // 111100110D00nnn0ddd00001N1M1mmm0 where Dddd=Qd, Nnnn=Qn, and Mmmm=Qm.
3323 // vmul<c>.<dt> <Qd>, <Qn>, <Qm>
3325 // 111100100Dssnnn0ddd01001NqM1mmm0 where Dddd=Qd, Nnnn=Qn, Mmmm=Qm, and
3358 const IValueT Qn = encodeQRegister(OpQn, "Qn", Vmull);
3362 const IValueT Dn = mapQRegToDReg(Qn);
3385 // vmull<c>.<dt> <Qd>, <Qn>, <Qm>
3402 const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vmull));
3433 const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vdup));
3479 const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vzip));
3515 // vmul.f32 <Qd>, <Qn>, <Qm>
3517 // 111100110D00nnn0ddd01101MqM1mmm0 where Dddd=Qd, Nnnn=Qn, and Mmmm=Qm.
3534 constexpr IValueT Qn = 0;
3538 emitSIMDBase(VmvnOpcode, mapQRegToDReg(Qd), mapQRegToDReg(Qn),
3554 const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vmov));
3580 const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vmov));
3606 const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vmov));
3632 const IValueT Dn = mapQRegToDReg(encodeQRegister(OpQn, "Qn", Vmov));
3659 constexpr IValueT Qn = 0;
3666 mapQRegToDReg(Qn), mapQRegToDReg(Qm), UseQRegs,
3673 // vorr <Qd>, <Qn>, <Qm>
3830 // vqadd<c><q>.s<size> {<Qd>,} <Qn>, <Qm>
3844 // vqadd<c><q>.s<size> {<Qd>,} <Qn>, <Qm>
3858 // vqsub<c><q>.s<size> {<Qd>,} <Qn>, <Qm>
3872 // vqsub<c><q>.s<size> {<Qd>,} <Qn>, <Qm>
3886 // vsub.<dt> <Qd>, <Qn>, <Qm>
3917 const IValueT Qn = encodeQRegister(OpQn, "Qn", Vqmovn);
3920 const IValueT Dn = mapQRegToDReg(Qn);
3933 } else if (Qn != Qd) {
3953 // vsub.f32 <Qd>, <Qn>, <Qm>
3955 // 111100100D10nnn0ddd01101N1M0mmm0 where Dddd=Qd, Nnnn=Qn, and Mmmm=Qm.
4011 // vshl Qd, Qm, Qn
4013 // 1111001U0Dssnnnndddd0100NQM0mmmm where Ddddd=Qd, Mmmmm=Qm, Nnnnn=Qn, 0=U,
4058 // vshl Qd, Qm, Qn
4060 // 1111001U0Dssnnnndddd0100NQM0mmmm where Ddddd=Qd, Mmmmm=Qm, Nnnnn=Qn, 1=U,
