Lines Matching defs:Opcode
207 void AssemblerMIPS32::emitRsRt(IValueT Opcode, const Operand *OpRs,
212 Opcode |= Rs << 21;
213 Opcode |= Rt << 16;
215 emitInst(Opcode);
218 void AssemblerMIPS32::emitRtRsImm16(IValueT Opcode, const Operand *OpRt,
224 Opcode |= Rs << 21;
225 Opcode |= Rt << 16;
226 Opcode |= Imm & 0xffff;
228 emitInst(Opcode);
231 void AssemblerMIPS32::emitRtRsImm16Rel(IValueT Opcode, const Operand *OpRt,
248 Opcode |= Rs << 21;
249 Opcode |= Rt << 16;
250 Opcode |= Imm16 & 0xffff;
252 emitInst(Opcode);
255 void AssemblerMIPS32::emitFtRsImm16(IValueT Opcode, const Operand *OpFt,
261 Opcode |= Rs << 21;
262 Opcode |= Ft << 16;
263 Opcode |= Imm & 0xffff;
265 emitInst(Opcode);
268 void AssemblerMIPS32::emitRdRtSa(IValueT Opcode, const Operand *OpRd,
274 Opcode |= Rt << 16;
275 Opcode |= Rd << 11;
276 Opcode |= (Sa & 0x1f) << 6;
278 emitInst(Opcode);
281 void AssemblerMIPS32::emitRdRsRt(IValueT Opcode, const Operand *OpRd,
288 Opcode |= Rs << 21;
289 Opcode |= Rt << 16;
290 Opcode |= Rd << 11;
292 emitInst(Opcode);
295 void AssemblerMIPS32::emitCOP1Fcmp(IValueT Opcode, FPInstDataFormat Format,
301 Opcode |= CC << 8;
302 Opcode |= Fs << 11;
303 Opcode |= Ft << 16;
304 Opcode |= Format << 21;
306 emitInst(Opcode);
309 void AssemblerMIPS32::emitCOP1FmtFsFd(IValueT Opcode, FPInstDataFormat Format,
315 Opcode |= Fd << 6;
316 Opcode |= Fs << 11;
317 Opcode |= Format << 21;
319 emitInst(Opcode);
322 void AssemblerMIPS32::emitCOP1FmtFtFsFd(IValueT Opcode, FPInstDataFormat Format,
331 Opcode |= Fd << 6;
332 Opcode |= Fs << 11;
333 Opcode |= Ft << 16;
334 Opcode |= Format << 21;
336 emitInst(Opcode);
339 void AssemblerMIPS32::emitCOP1FmtRtFsFd(IValueT Opcode, FPInstDataFormat Format,
348 Opcode |= Fd << 6;
349 Opcode |= Fs << 11;
350 Opcode |= Rt << 16;
351 Opcode |= Format << 21;
353 emitInst(Opcode);
356 void AssemblerMIPS32::emitCOP1MovRtFs(IValueT Opcode, const Operand *OpRt,
361 Opcode |= Fs << 11;
362 Opcode |= Rt << 16;
364 emitInst(Opcode);
368 static constexpr IValueT Opcode = 0x44000005;
369 emitCOP1FmtFsFd(Opcode, DoublePrecision, OpFd, OpFs, "abs.d");
373 static constexpr IValueT Opcode = 0x44000005;
374 emitCOP1FmtFsFd(Opcode, SinglePrecision, OpFd, OpFs, "abs.s");
379 static constexpr IValueT Opcode = 0x20000000;
380 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "addi");
385 static constexpr IValueT Opcode = 0x44000000;
386 emitCOP1FmtFtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "add.d");
391 static constexpr IValueT Opcode = 0x44000000;
392 emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "add.s");
397 static constexpr IValueT Opcode = 0x24000000;
398 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "addiu");
403 static constexpr IValueT Opcode = 0x24000000;
404 emitRtRsImm16Rel(Opcode, OpRt, OpRs, OpImm, Reloc, "addiu");
409 static constexpr IValueT Opcode = 0x00000021;
410 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "addu");
415 static constexpr IValueT Opcode = 0x00000024;
416 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "and");
421 static constexpr IValueT Opcode = 0x30000000;
422 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "andi");
442 static constexpr IValueT Opcode = 0x44000032;
443 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
448 static constexpr IValueT Opcode = 0x44000032;
449 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
454 static constexpr IValueT Opcode = 0x44000036;
455 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
460 static constexpr IValueT Opcode = 0x44000036;
461 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
466 static constexpr IValueT Opcode = 0x44000034;
467 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
472 static constexpr IValueT Opcode = 0x44000034;
473 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
478 static constexpr IValueT Opcode = 0x44000033;
479 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
484 static constexpr IValueT Opcode = 0x44000033;
485 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
490 static constexpr IValueT Opcode = 0x44000037;
491 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
496 static constexpr IValueT Opcode
497 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
502 static constexpr IValueT Opcode = 0x44000035;
503 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
508 static constexpr IValueT Opcode = 0x44000035;
509 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
514 static constexpr IValueT Opcode = 0x44000031;
515 emitCOP1Fcmp(Opcode, DoublePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
520 static constexpr IValueT Opcode = 0x44000031;
521 emitCOP1Fcmp(Opcode, SinglePrecision, OpFs, OpFt, OperandMIPS32FCC::FCC0,
526 IValueT Opcode = 0x70000020;
529 Opcode |= Rd << 11;
530 Opcode |= Rd << 16;
531 Opcode |= Rs << 21;
532 emitInst(Opcode);
536 static constexpr IValueT Opcode = 0x44000021;
537 emitCOP1FmtFsFd(Opcode, Long, OpFd, OpFs, "cvt.d.l");
541 static constexpr IValueT Opcode = 0x44000021;
542 emitCOP1FmtFsFd(Opcode, SinglePrecision, OpFd, OpFs, "cvt.d.s");
546 static constexpr IValueT Opcode = 0x44000021;
547 emitCOP1FmtFsFd(Opcode, Word, OpFd, OpFs, "cvt.d.w");
551 static constexpr IValueT Opcode = 0x44000020;
552 emitCOP1FmtFsFd(Opcode, DoublePrecision, OpFd, OpFs, "cvt.s.d");
556 static constexpr IValueT Opcode = 0x44000020;
557 emitCOP1FmtFsFd(Opcode, Long, OpFd, OpFs, "cvt.s.l");
561 static constexpr IValueT Opcode = 0x44000020;
562 emitCOP1FmtFsFd(Opcode, Word, OpFd, OpFs, "cvt.s.w");
566 static constexpr IValueT Opcode = 0x0000001A;
567 emitRsRt(Opcode, OpRs, OpRt, "div");
572 static constexpr IValueT Opcode = 0x44000003;
573 emitCOP1FmtFtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "div.d");
578 static constexpr IValueT Opcode = 0x44000003;
579 emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "div.s");
583 static constexpr IValueT Opcode = 0x0000001B;
584 emitRsRt(Opcode, OpRs, OpRt, "divu");
648 IValueT Opcode = 0x0C000000;
650 emitInst(Opcode);
655 IValueT Opcode = 0x00000009;
659 Opcode |= Rd << 11;
660 Opcode |= Rs << 21;
661 emitInst(Opcode);
667 IValueT Opcode = 0x3C000000;
679 Opcode |= Rt << 16;
680 Opcode |= Imm16;
681 emitInst(Opcode);
686 IValueT Opcode = 0xD4000000;
699 Opcode |= Base << 21;
700 Opcode |= Rt << 16;
701 Opcode |= Imm16;
702 emitInst(Opcode);
707 static constexpr IValueT Opcode = 0xC0000000;
708 emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "ll");
716 static constexpr IValueT Opcode = 0x80000000;
717 emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "lb");
721 static constexpr IValueT Opcode = 0x84000000;
722 emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "lh");
726 static constexpr IValueT Opcode = 0x8C000000;
727 emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "lw");
731 static constexpr IValueT Opcode = 0xC4000000;
732 emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "lwc1");
736 static constexpr IValueT Opcode = 0xD4000000;
737 emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "ldc1");
746 IValueT Opcode = 0xC4000000;
759 Opcode |= Base << 21;
760 Opcode |= Rt << 16;
761 Opcode |= Imm16;
762 emitInst(Opcode);
766 static constexpr IValueT Opcode = 0x44000000;
767 emitCOP1MovRtFs(Opcode, OpRt, OpFs, "mfc1");
771 IValueT Opcode = 0x000000010;
773 Opcode |= Rd << 11;
774 emitInst(Opcode);
778 IValueT Opcode = 0x000000012;
780 Opcode |= Rd << 11;
781 emitInst(Opcode);
785 static constexpr IValueT Opcode = 0x44000006;
786 emitCOP1FmtFsFd(Opcode, DoublePrecision, OpFd, OpFs, "mov.d");
790 static constexpr IValueT Opcode = 0x44000006;
791 emitCOP1FmtFsFd(Opcode, SinglePrecision, OpFd, OpFs, "mov.s");
818 IValueT Opcode = 0x00000021;
822 Opcode |= Rs << 21;
823 Opcode |= Rt << 16;
824 Opcode |= Rd << 11;
825 emitInst(Opcode);
835 IValueT Opcode = 0x00000001;
843 Opcode |= Rd << 11;
844 Opcode |= InstEncodingFalse << 16;
845 Opcode |= Cc << 18;
846 Opcode |= Rs << 21;
847 emitInst(Opcode);
852 static constexpr IValueT Opcode = 0x0000000B;
853 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "movn");
858 static constexpr IValueT Opcode = 0x44000013;
859 emitCOP1FmtRtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "movn.d");
864 static constexpr IValueT Opcode = 0x44000013;
865 emitCOP1FmtRtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movn.s");
870 IValueT Opcode = 0x00000001;
878 Opcode |= Rd << 11;
879 Opcode |= InstEncodingTrue << 16;
880 Opcode |= Cc << 18;
881 Opcode |= Rs << 21;
882 emitInst(Opcode);
887 static constexpr IValueT Opcode = 0x44000012;
888 emitCOP1FmtFtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "movz.d");
893 static constexpr IValueT Opcode = 0x0000000A;
894 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "movz");
899 static constexpr IValueT Opcode = 0x44000012;
900 emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "movz.s");
904 static constexpr IValueT Opcode = 0x44800000;
905 emitCOP1MovRtFs(Opcode, OpRt, OpFs, "mtc1");
909 IValueT Opcode = 0x000000011;
911 Opcode |= Rs << 21;
912 emitInst(Opcode);
916 IValueT Opcode = 0x000000013;
918 Opcode |= Rs << 21;
919 emitInst(Opcode);
924 static constexpr IValueT Opcode = 0x70000002;
925 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "mul");
930 static constexpr IValueT Opcode = 0x44000002;
931 emitCOP1FmtFtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "mul.d");
936 static constexpr IValueT Opcode = 0x44000002;
937 emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "mul.s");
941 static constexpr IValueT Opcode = 0x00000018;
942 emitRsRt(Opcode, OpRs, OpRt, "mult");
946 static constexpr IValueT Opcode = 0x00000019;
947 emitRsRt(Opcode, OpRs, OpRt, "multu");
952 static constexpr IValueT Opcode = 0x00000027;
953 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "nor");
958 static constexpr IValueT Opcode = 0x00000025;
959 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "or");
964 static constexpr IValueT Opcode = 0x34000000;
965 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "ori");
969 static constexpr IValueT Opcode = 0x03E00008; // JR $31
970 emitInst(Opcode);
976 static constexpr IValueT Opcode = 0xE0000000;
977 emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sc");
982 static constexpr IValueT Opcode = 0x00000000;
983 emitRdRtSa(Opcode, OpRd, OpRt, Sa, "sll");
988 static constexpr IValueT Opcode = 0x00000004;
989 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "sllv");
994 static constexpr IValueT Opcode = 0x0000002A;
995 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "slt");
1000 static constexpr IValueT Opcode = 0x28000000;
1001 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "slti");
1006 static constexpr IValueT Opcode = 0x0000002B;
1007 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "sltu");
1012 static constexpr IValueT Opcode = 0x2c000000;
1013 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "sltiu");
1017 static constexpr IValueT Opcode = 0x44000004;
1018 emitCOP1FmtFsFd(Opcode, DoublePrecision, OpFd, OpFs, "sqrt.d");
1022 static constexpr IValueT Opcode = 0x44000004;
1023 emitCOP1FmtFsFd(Opcode, SinglePrecision, OpFd, OpFs, "sqrt.s");
1028 static constexpr IValueT Opcode = 0x00000003;
1029 emitRdRtSa(Opcode, OpRd, OpRt, Sa, "sra");
1034 static constexpr IValueT Opcode = 0x00000002;
1035 emitRdRtSa(Opcode, OpRd, OpRt, Sa, "srl");
1040 static constexpr IValueT Opcode = 0x00000007;
1041 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "srav");
1046 static constexpr IValueT Opcode = 0x00000006;
1047 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "srlv");
1052 static constexpr IValueT Opcode = 0x44000001;
1053 emitCOP1FmtFtFsFd(Opcode, DoublePrecision, OpFd, OpFs, OpFt, "sub.d");
1058 static constexpr IValueT Opcode = 0x44000001;
1059 emitCOP1FmtFtFsFd(Opcode, SinglePrecision, OpFd, OpFs, OpFt, "sub.s");
1064 static constexpr IValueT Opcode = 0x00000023;
1065 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "subu");
1070 IValueT Opcode = 0xF4000000;
1083 Opcode |= Base << 21;
1084 Opcode |= Rt << 16;
1085 Opcode |= Imm16;
1086 emitInst(Opcode);
1094 static constexpr IValueT Opcode = 0xA0000000;
1095 emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sb");
1099 static constexpr IValueT Opcode = 0xA4000000;
1100 emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sh");
1104 static constexpr IValueT Opcode = 0xAC000000;
1105 emitRtRsImm16(Opcode, OpRt, OpBase, Offset, "sw");
1109 static constexpr IValueT Opcode = 0xE4000000;
1110 emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "swc1");
1114 static constexpr IValueT Opcode = 0xF4000000;
1115 emitFtRsImm16(Opcode, OpRt, OpBase, Offset, "sdc1");
1124 IValueT Opcode = 0xE4000000;
1137 Opcode |= Base << 21;
1138 Opcode |= Rt << 16;
1139 Opcode |= Imm16;
1140 emitInst(Opcode);
1144 static constexpr IValueT Opcode = 0x0000000f;
1145 emitInst(Opcode);
1150 IValueT Opcode = 0x00000034;
1153 Opcode |= (TrapCode & 0xFFFFF) << 6;
1154 Opcode |= Rt << 16;
1155 Opcode |= Rs << 21;
1156 emitInst(Opcode);
1160 static constexpr IValueT Opcode = 0x4400000D;
1161 emitCOP1FmtFsFd(Opcode, Long, OpFd, OpFs, "trunc.l.d");
1165 static constexpr IValueT Opcode = 0x4400000D;
1166 emitCOP1FmtFsFd(Opcode, Long, OpFd, OpFs, "trunc.l.s");
1170 static constexpr IValueT Opcode = 0x4400000D;
1171 emitCOP1FmtFsFd(Opcode, DoublePrecision, OpFd, OpFs, "trunc.w.d");
1175 static constexpr IValueT Opcode = 0x4400000D;
1176 emitCOP1FmtFsFd(Opcode, SinglePrecision, OpFd, OpFs, "trunc.w.s");
1181 static constexpr IValueT Opcode = 0x00000026;
1182 emitRdRsRt(Opcode, OpRd, OpRs, OpRt, "xor");
1187 static constexpr IValueT Opcode = 0x38000000;
1188 emitRtRsImm16(Opcode, OpRt, OpRs, Imm, "xori");
1193 IValueT Opcode = 0;
1201 Opcode = 0x10000000;
1205 Opcode = 0x14000000;
1208 Opcode = 0x18000000;
1211 Opcode = 0x04000000;
1214 Opcode = 0x04010000;
1217 Opcode = 0x1C000000;
1221 if (Opcode == 0) {
1227 Opcode |= Rs << 21;
1232 Opcode |= Rt << 16;
1235 Opcode = encodeBranchOffset(Offset, Opcode);
1236 emitInst(Opcode);
